bl602_pac/rf/
lo_reg_ctrl_hw1.rs1#[doc = "Register `lo_reg_ctrl_hw1` reader"]
2pub struct R(crate::R<LO_REG_CTRL_HW1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<LO_REG_CTRL_HW1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<LO_REG_CTRL_HW1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<LO_REG_CTRL_HW1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `lo_reg_ctrl_hw1` writer"]
17pub struct W(crate::W<LO_REG_CTRL_HW1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<LO_REG_CTRL_HW1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<LO_REG_CTRL_HW1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<LO_REG_CTRL_HW1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `lo_fbdv_halfstep_en_rx` reader - "]
38pub type LO_FBDV_HALFSTEP_EN_RX_R = crate::BitReader<bool>;
39#[doc = "Field `lo_fbdv_halfstep_en_rx` writer - "]
40pub type LO_FBDV_HALFSTEP_EN_RX_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, bool, O>;
42#[doc = "Field `lo_fbdv_halfstep_en_tx` reader - "]
43pub type LO_FBDV_HALFSTEP_EN_TX_R = crate::BitReader<bool>;
44#[doc = "Field `lo_fbdv_halfstep_en_tx` writer - "]
45pub type LO_FBDV_HALFSTEP_EN_TX_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, bool, O>;
47#[doc = "Field `lo_cp_sel_rx` reader - "]
48pub type LO_CP_SEL_RX_R = crate::BitReader<bool>;
49#[doc = "Field `lo_cp_sel_rx` writer - "]
50pub type LO_CP_SEL_RX_W<'a, const O: u8> = crate::BitWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, bool, O>;
51#[doc = "Field `lo_cp_sel_tx` reader - "]
52pub type LO_CP_SEL_TX_R = crate::BitReader<bool>;
53#[doc = "Field `lo_cp_sel_tx` writer - "]
54pub type LO_CP_SEL_TX_W<'a, const O: u8> = crate::BitWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, bool, O>;
55#[doc = "Field `lo_lf_cz_rx` reader - "]
56pub type LO_LF_CZ_RX_R = crate::FieldReader<u8, u8>;
57#[doc = "Field `lo_lf_cz_rx` writer - "]
58pub type LO_LF_CZ_RX_W<'a, const O: u8> =
59 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
60#[doc = "Field `lo_lf_cz_tx` reader - "]
61pub type LO_LF_CZ_TX_R = crate::FieldReader<u8, u8>;
62#[doc = "Field `lo_lf_cz_tx` writer - "]
63pub type LO_LF_CZ_TX_W<'a, const O: u8> =
64 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
65#[doc = "Field `lo_lf_rz_rx` reader - "]
66pub type LO_LF_RZ_RX_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `lo_lf_rz_rx` writer - "]
68pub type LO_LF_RZ_RX_W<'a, const O: u8> =
69 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
70#[doc = "Field `lo_lf_rz_tx` reader - "]
71pub type LO_LF_RZ_TX_R = crate::FieldReader<u8, u8>;
72#[doc = "Field `lo_lf_rz_tx` writer - "]
73pub type LO_LF_RZ_TX_W<'a, const O: u8> =
74 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
75#[doc = "Field `lo_lf_r4_rx` reader - "]
76pub type LO_LF_R4_RX_R = crate::FieldReader<u8, u8>;
77#[doc = "Field `lo_lf_r4_rx` writer - "]
78pub type LO_LF_R4_RX_W<'a, const O: u8> =
79 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
80#[doc = "Field `lo_lf_r4_tx` reader - "]
81pub type LO_LF_R4_TX_R = crate::FieldReader<u8, u8>;
82#[doc = "Field `lo_lf_r4_tx` writer - "]
83pub type LO_LF_R4_TX_W<'a, const O: u8> =
84 crate::FieldWriter<'a, u32, LO_REG_CTRL_HW1_SPEC, u8, u8, 2, O>;
85impl R {
86 #[doc = "Bit 0"]
87 #[inline(always)]
88 pub fn lo_fbdv_halfstep_en_rx(&self) -> LO_FBDV_HALFSTEP_EN_RX_R {
89 LO_FBDV_HALFSTEP_EN_RX_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1"]
92 #[inline(always)]
93 pub fn lo_fbdv_halfstep_en_tx(&self) -> LO_FBDV_HALFSTEP_EN_TX_R {
94 LO_FBDV_HALFSTEP_EN_TX_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bit 2"]
97 #[inline(always)]
98 pub fn lo_cp_sel_rx(&self) -> LO_CP_SEL_RX_R {
99 LO_CP_SEL_RX_R::new(((self.bits >> 2) & 1) != 0)
100 }
101 #[doc = "Bit 3"]
102 #[inline(always)]
103 pub fn lo_cp_sel_tx(&self) -> LO_CP_SEL_TX_R {
104 LO_CP_SEL_TX_R::new(((self.bits >> 3) & 1) != 0)
105 }
106 #[doc = "Bits 4:5"]
107 #[inline(always)]
108 pub fn lo_lf_cz_rx(&self) -> LO_LF_CZ_RX_R {
109 LO_LF_CZ_RX_R::new(((self.bits >> 4) & 3) as u8)
110 }
111 #[doc = "Bits 8:9"]
112 #[inline(always)]
113 pub fn lo_lf_cz_tx(&self) -> LO_LF_CZ_TX_R {
114 LO_LF_CZ_TX_R::new(((self.bits >> 8) & 3) as u8)
115 }
116 #[doc = "Bits 12:13"]
117 #[inline(always)]
118 pub fn lo_lf_rz_rx(&self) -> LO_LF_RZ_RX_R {
119 LO_LF_RZ_RX_R::new(((self.bits >> 12) & 3) as u8)
120 }
121 #[doc = "Bits 16:17"]
122 #[inline(always)]
123 pub fn lo_lf_rz_tx(&self) -> LO_LF_RZ_TX_R {
124 LO_LF_RZ_TX_R::new(((self.bits >> 16) & 3) as u8)
125 }
126 #[doc = "Bits 20:21"]
127 #[inline(always)]
128 pub fn lo_lf_r4_rx(&self) -> LO_LF_R4_RX_R {
129 LO_LF_R4_RX_R::new(((self.bits >> 20) & 3) as u8)
130 }
131 #[doc = "Bits 24:25"]
132 #[inline(always)]
133 pub fn lo_lf_r4_tx(&self) -> LO_LF_R4_TX_R {
134 LO_LF_R4_TX_R::new(((self.bits >> 24) & 3) as u8)
135 }
136}
137impl W {
138 #[doc = "Bit 0"]
139 #[inline(always)]
140 #[must_use]
141 pub fn lo_fbdv_halfstep_en_rx(&mut self) -> LO_FBDV_HALFSTEP_EN_RX_W<0> {
142 LO_FBDV_HALFSTEP_EN_RX_W::new(self)
143 }
144 #[doc = "Bit 1"]
145 #[inline(always)]
146 #[must_use]
147 pub fn lo_fbdv_halfstep_en_tx(&mut self) -> LO_FBDV_HALFSTEP_EN_TX_W<1> {
148 LO_FBDV_HALFSTEP_EN_TX_W::new(self)
149 }
150 #[doc = "Bit 2"]
151 #[inline(always)]
152 #[must_use]
153 pub fn lo_cp_sel_rx(&mut self) -> LO_CP_SEL_RX_W<2> {
154 LO_CP_SEL_RX_W::new(self)
155 }
156 #[doc = "Bit 3"]
157 #[inline(always)]
158 #[must_use]
159 pub fn lo_cp_sel_tx(&mut self) -> LO_CP_SEL_TX_W<3> {
160 LO_CP_SEL_TX_W::new(self)
161 }
162 #[doc = "Bits 4:5"]
163 #[inline(always)]
164 #[must_use]
165 pub fn lo_lf_cz_rx(&mut self) -> LO_LF_CZ_RX_W<4> {
166 LO_LF_CZ_RX_W::new(self)
167 }
168 #[doc = "Bits 8:9"]
169 #[inline(always)]
170 #[must_use]
171 pub fn lo_lf_cz_tx(&mut self) -> LO_LF_CZ_TX_W<8> {
172 LO_LF_CZ_TX_W::new(self)
173 }
174 #[doc = "Bits 12:13"]
175 #[inline(always)]
176 #[must_use]
177 pub fn lo_lf_rz_rx(&mut self) -> LO_LF_RZ_RX_W<12> {
178 LO_LF_RZ_RX_W::new(self)
179 }
180 #[doc = "Bits 16:17"]
181 #[inline(always)]
182 #[must_use]
183 pub fn lo_lf_rz_tx(&mut self) -> LO_LF_RZ_TX_W<16> {
184 LO_LF_RZ_TX_W::new(self)
185 }
186 #[doc = "Bits 20:21"]
187 #[inline(always)]
188 #[must_use]
189 pub fn lo_lf_r4_rx(&mut self) -> LO_LF_R4_RX_W<20> {
190 LO_LF_R4_RX_W::new(self)
191 }
192 #[doc = "Bits 24:25"]
193 #[inline(always)]
194 #[must_use]
195 pub fn lo_lf_r4_tx(&mut self) -> LO_LF_R4_TX_W<24> {
196 LO_LF_R4_TX_W::new(self)
197 }
198 #[doc = "Writes raw bits to the register."]
199 #[inline(always)]
200 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
201 self.0.bits(bits);
202 self
203 }
204}
205#[doc = "lo_reg_ctrl_hw1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lo_reg_ctrl_hw1](index.html) module"]
206pub struct LO_REG_CTRL_HW1_SPEC;
207impl crate::RegisterSpec for LO_REG_CTRL_HW1_SPEC {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [lo_reg_ctrl_hw1::R](R) reader structure"]
211impl crate::Readable for LO_REG_CTRL_HW1_SPEC {
212 type Reader = R;
213}
214#[doc = "`write(|w| ..)` method takes [lo_reg_ctrl_hw1::W](W) writer structure"]
215impl crate::Writable for LO_REG_CTRL_HW1_SPEC {
216 type Writer = W;
217 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
218 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
219}
220#[doc = "`reset()` method sets lo_reg_ctrl_hw1 to value 0"]
221impl crate::Resettable for LO_REG_CTRL_HW1_SPEC {
222 const RESET_VALUE: Self::Ux = 0;
223}