bl602_pac/rf/
dfe_ctrl_0.rs

1#[doc = "Register `dfe_ctrl_0` reader"]
2pub struct R(crate::R<DFE_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DFE_CTRL_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DFE_CTRL_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DFE_CTRL_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `dfe_ctrl_0` writer"]
17pub struct W(crate::W<DFE_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DFE_CTRL_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DFE_CTRL_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DFE_CTRL_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `tx_iqc_phase` reader - "]
38pub type TX_IQC_PHASE_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `tx_iqc_phase` writer - "]
40pub type TX_IQC_PHASE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, DFE_CTRL_0_SPEC, u16, u16, 10, O>;
42#[doc = "Field `tx_iqc_phase_en` reader - "]
43pub type TX_IQC_PHASE_EN_R = crate::BitReader<bool>;
44#[doc = "Field `tx_iqc_phase_en` writer - "]
45pub type TX_IQC_PHASE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFE_CTRL_0_SPEC, bool, O>;
46#[doc = "Field `tx_iqc_gain` reader - "]
47pub type TX_IQC_GAIN_R = crate::FieldReader<u16, u16>;
48#[doc = "Field `tx_iqc_gain` writer - "]
49pub type TX_IQC_GAIN_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, DFE_CTRL_0_SPEC, u16, u16, 11, O>;
51#[doc = "Field `tx_iqc_gain_en` reader - "]
52pub type TX_IQC_GAIN_EN_R = crate::BitReader<bool>;
53#[doc = "Field `tx_iqc_gain_en` writer - "]
54pub type TX_IQC_GAIN_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFE_CTRL_0_SPEC, bool, O>;
55#[doc = "Field `tx_dvga_gain_qdb` reader - "]
56pub type TX_DVGA_GAIN_QDB_R = crate::FieldReader<u8, u8>;
57#[doc = "Field `tx_dvga_gain_qdb` writer - "]
58pub type TX_DVGA_GAIN_QDB_W<'a, const O: u8> =
59    crate::FieldWriter<'a, u32, DFE_CTRL_0_SPEC, u8, u8, 7, O>;
60#[doc = "Field `tx_dvga_gain_ctrl_hw` reader - "]
61pub type TX_DVGA_GAIN_CTRL_HW_R = crate::BitReader<bool>;
62#[doc = "Field `tx_dvga_gain_ctrl_hw` writer - "]
63pub type TX_DVGA_GAIN_CTRL_HW_W<'a, const O: u8> =
64    crate::BitWriter<'a, u32, DFE_CTRL_0_SPEC, bool, O>;
65impl R {
66    #[doc = "Bits 0:9"]
67    #[inline(always)]
68    pub fn tx_iqc_phase(&self) -> TX_IQC_PHASE_R {
69        TX_IQC_PHASE_R::new((self.bits & 0x03ff) as u16)
70    }
71    #[doc = "Bit 10"]
72    #[inline(always)]
73    pub fn tx_iqc_phase_en(&self) -> TX_IQC_PHASE_EN_R {
74        TX_IQC_PHASE_EN_R::new(((self.bits >> 10) & 1) != 0)
75    }
76    #[doc = "Bits 12:22"]
77    #[inline(always)]
78    pub fn tx_iqc_gain(&self) -> TX_IQC_GAIN_R {
79        TX_IQC_GAIN_R::new(((self.bits >> 12) & 0x07ff) as u16)
80    }
81    #[doc = "Bit 23"]
82    #[inline(always)]
83    pub fn tx_iqc_gain_en(&self) -> TX_IQC_GAIN_EN_R {
84        TX_IQC_GAIN_EN_R::new(((self.bits >> 23) & 1) != 0)
85    }
86    #[doc = "Bits 24:30"]
87    #[inline(always)]
88    pub fn tx_dvga_gain_qdb(&self) -> TX_DVGA_GAIN_QDB_R {
89        TX_DVGA_GAIN_QDB_R::new(((self.bits >> 24) & 0x7f) as u8)
90    }
91    #[doc = "Bit 31"]
92    #[inline(always)]
93    pub fn tx_dvga_gain_ctrl_hw(&self) -> TX_DVGA_GAIN_CTRL_HW_R {
94        TX_DVGA_GAIN_CTRL_HW_R::new(((self.bits >> 31) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bits 0:9"]
99    #[inline(always)]
100    #[must_use]
101    pub fn tx_iqc_phase(&mut self) -> TX_IQC_PHASE_W<0> {
102        TX_IQC_PHASE_W::new(self)
103    }
104    #[doc = "Bit 10"]
105    #[inline(always)]
106    #[must_use]
107    pub fn tx_iqc_phase_en(&mut self) -> TX_IQC_PHASE_EN_W<10> {
108        TX_IQC_PHASE_EN_W::new(self)
109    }
110    #[doc = "Bits 12:22"]
111    #[inline(always)]
112    #[must_use]
113    pub fn tx_iqc_gain(&mut self) -> TX_IQC_GAIN_W<12> {
114        TX_IQC_GAIN_W::new(self)
115    }
116    #[doc = "Bit 23"]
117    #[inline(always)]
118    #[must_use]
119    pub fn tx_iqc_gain_en(&mut self) -> TX_IQC_GAIN_EN_W<23> {
120        TX_IQC_GAIN_EN_W::new(self)
121    }
122    #[doc = "Bits 24:30"]
123    #[inline(always)]
124    #[must_use]
125    pub fn tx_dvga_gain_qdb(&mut self) -> TX_DVGA_GAIN_QDB_W<24> {
126        TX_DVGA_GAIN_QDB_W::new(self)
127    }
128    #[doc = "Bit 31"]
129    #[inline(always)]
130    #[must_use]
131    pub fn tx_dvga_gain_ctrl_hw(&mut self) -> TX_DVGA_GAIN_CTRL_HW_W<31> {
132        TX_DVGA_GAIN_CTRL_HW_W::new(self)
133    }
134    #[doc = "Writes raw bits to the register."]
135    #[inline(always)]
136    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
137        self.0.bits(bits);
138        self
139    }
140}
141#[doc = "dfe_ctrl_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfe_ctrl_0](index.html) module"]
142pub struct DFE_CTRL_0_SPEC;
143impl crate::RegisterSpec for DFE_CTRL_0_SPEC {
144    type Ux = u32;
145}
146#[doc = "`read()` method returns [dfe_ctrl_0::R](R) reader structure"]
147impl crate::Readable for DFE_CTRL_0_SPEC {
148    type Reader = R;
149}
150#[doc = "`write(|w| ..)` method takes [dfe_ctrl_0::W](W) writer structure"]
151impl crate::Writable for DFE_CTRL_0_SPEC {
152    type Writer = W;
153    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
154    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
155}
156#[doc = "`reset()` method sets dfe_ctrl_0 to value 0"]
157impl crate::Resettable for DFE_CTRL_0_SPEC {
158    const RESET_VALUE: Self::Ux = 0;
159}
bl602_pac/rf/dfe_ctrl_0.rs

bl602_pac/rf/
dfe_ctrl_0.rs
