bl602_pac/l1c/
l1c_config.rs1#[doc = "Register `l1c_config` reader"]
2pub struct R(crate::R<L1C_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<L1C_CONFIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<L1C_CONFIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<L1C_CONFIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `l1c_config` writer"]
17pub struct W(crate::W<L1C_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<L1C_CONFIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<L1C_CONFIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<L1C_CONFIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `l1c_cacheable` reader - "]
38pub type L1C_CACHEABLE_R = crate::BitReader<bool>;
39#[doc = "Field `l1c_cacheable` writer - "]
40pub type L1C_CACHEABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
41#[doc = "Field `l1c_cnt_en` reader - "]
42pub type L1C_CNT_EN_R = crate::BitReader<bool>;
43#[doc = "Field `l1c_cnt_en` writer - "]
44pub type L1C_CNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
45#[doc = "Field `l1c_invalid_en` reader - "]
46pub type L1C_INVALID_EN_R = crate::BitReader<bool>;
47#[doc = "Field `l1c_invalid_en` writer - "]
48pub type L1C_INVALID_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
49#[doc = "Field `l1c_invalid_done` reader - "]
50pub type L1C_INVALID_DONE_R = crate::BitReader<bool>;
51#[doc = "Field `l1c_way_dis` reader - "]
52pub type L1C_WAY_DIS_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `l1c_way_dis` writer - "]
54pub type L1C_WAY_DIS_W<'a, const O: u8> =
55 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 4, O>;
56#[doc = "Field `irom_2t_access` reader - "]
57pub type IROM_2T_ACCESS_R = crate::BitReader<bool>;
58#[doc = "Field `irom_2t_access` writer - "]
59pub type IROM_2T_ACCESS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
60#[doc = "Field `l1c_bypass` reader - "]
61pub type L1C_BYPASS_R = crate::BitReader<bool>;
62#[doc = "Field `l1c_bypass` writer - "]
63pub type L1C_BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
64#[doc = "Field `l1c_bmx_err_en` reader - "]
65pub type L1C_BMX_ERR_EN_R = crate::BitReader<bool>;
66#[doc = "Field `l1c_bmx_err_en` writer - "]
67pub type L1C_BMX_ERR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
68#[doc = "Field `l1c_bmx_arb_mode` reader - "]
69pub type L1C_BMX_ARB_MODE_R = crate::FieldReader<u8, u8>;
70#[doc = "Field `l1c_bmx_arb_mode` writer - "]
71pub type L1C_BMX_ARB_MODE_W<'a, const O: u8> =
72 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 2, O>;
73#[doc = "Field `l1c_bmx_timeout_en` reader - "]
74pub type L1C_BMX_TIMEOUT_EN_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `l1c_bmx_timeout_en` writer - "]
76pub type L1C_BMX_TIMEOUT_EN_W<'a, const O: u8> =
77 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 4, O>;
78#[doc = "Field `l1c_bmx_busy_option_dis` reader - "]
79pub type L1C_BMX_BUSY_OPTION_DIS_R = crate::BitReader<bool>;
80#[doc = "Field `l1c_bmx_busy_option_dis` writer - "]
81pub type L1C_BMX_BUSY_OPTION_DIS_W<'a, const O: u8> =
82 crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
83#[doc = "Field `early_resp_dis` reader - "]
84pub type EARLY_RESP_DIS_R = crate::BitReader<bool>;
85#[doc = "Field `early_resp_dis` writer - "]
86pub type EARLY_RESP_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
87#[doc = "Field `wrap_dis` reader - "]
88pub type WRAP_DIS_R = crate::BitReader<bool>;
89#[doc = "Field `wrap_dis` writer - "]
90pub type WRAP_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
91impl R {
92 #[doc = "Bit 0"]
93 #[inline(always)]
94 pub fn l1c_cacheable(&self) -> L1C_CACHEABLE_R {
95 L1C_CACHEABLE_R::new((self.bits & 1) != 0)
96 }
97 #[doc = "Bit 1"]
98 #[inline(always)]
99 pub fn l1c_cnt_en(&self) -> L1C_CNT_EN_R {
100 L1C_CNT_EN_R::new(((self.bits >> 1) & 1) != 0)
101 }
102 #[doc = "Bit 2"]
103 #[inline(always)]
104 pub fn l1c_invalid_en(&self) -> L1C_INVALID_EN_R {
105 L1C_INVALID_EN_R::new(((self.bits >> 2) & 1) != 0)
106 }
107 #[doc = "Bit 3"]
108 #[inline(always)]
109 pub fn l1c_invalid_done(&self) -> L1C_INVALID_DONE_R {
110 L1C_INVALID_DONE_R::new(((self.bits >> 3) & 1) != 0)
111 }
112 #[doc = "Bits 8:11"]
113 #[inline(always)]
114 pub fn l1c_way_dis(&self) -> L1C_WAY_DIS_R {
115 L1C_WAY_DIS_R::new(((self.bits >> 8) & 0x0f) as u8)
116 }
117 #[doc = "Bit 12"]
118 #[inline(always)]
119 pub fn irom_2t_access(&self) -> IROM_2T_ACCESS_R {
120 IROM_2T_ACCESS_R::new(((self.bits >> 12) & 1) != 0)
121 }
122 #[doc = "Bit 14"]
123 #[inline(always)]
124 pub fn l1c_bypass(&self) -> L1C_BYPASS_R {
125 L1C_BYPASS_R::new(((self.bits >> 14) & 1) != 0)
126 }
127 #[doc = "Bit 15"]
128 #[inline(always)]
129 pub fn l1c_bmx_err_en(&self) -> L1C_BMX_ERR_EN_R {
130 L1C_BMX_ERR_EN_R::new(((self.bits >> 15) & 1) != 0)
131 }
132 #[doc = "Bits 16:17"]
133 #[inline(always)]
134 pub fn l1c_bmx_arb_mode(&self) -> L1C_BMX_ARB_MODE_R {
135 L1C_BMX_ARB_MODE_R::new(((self.bits >> 16) & 3) as u8)
136 }
137 #[doc = "Bits 20:23"]
138 #[inline(always)]
139 pub fn l1c_bmx_timeout_en(&self) -> L1C_BMX_TIMEOUT_EN_R {
140 L1C_BMX_TIMEOUT_EN_R::new(((self.bits >> 20) & 0x0f) as u8)
141 }
142 #[doc = "Bit 24"]
143 #[inline(always)]
144 pub fn l1c_bmx_busy_option_dis(&self) -> L1C_BMX_BUSY_OPTION_DIS_R {
145 L1C_BMX_BUSY_OPTION_DIS_R::new(((self.bits >> 24) & 1) != 0)
146 }
147 #[doc = "Bit 25"]
148 #[inline(always)]
149 pub fn early_resp_dis(&self) -> EARLY_RESP_DIS_R {
150 EARLY_RESP_DIS_R::new(((self.bits >> 25) & 1) != 0)
151 }
152 #[doc = "Bit 26"]
153 #[inline(always)]
154 pub fn wrap_dis(&self) -> WRAP_DIS_R {
155 WRAP_DIS_R::new(((self.bits >> 26) & 1) != 0)
156 }
157}
158impl W {
159 #[doc = "Bit 0"]
160 #[inline(always)]
161 #[must_use]
162 pub fn l1c_cacheable(&mut self) -> L1C_CACHEABLE_W<0> {
163 L1C_CACHEABLE_W::new(self)
164 }
165 #[doc = "Bit 1"]
166 #[inline(always)]
167 #[must_use]
168 pub fn l1c_cnt_en(&mut self) -> L1C_CNT_EN_W<1> {
169 L1C_CNT_EN_W::new(self)
170 }
171 #[doc = "Bit 2"]
172 #[inline(always)]
173 #[must_use]
174 pub fn l1c_invalid_en(&mut self) -> L1C_INVALID_EN_W<2> {
175 L1C_INVALID_EN_W::new(self)
176 }
177 #[doc = "Bits 8:11"]
178 #[inline(always)]
179 #[must_use]
180 pub fn l1c_way_dis(&mut self) -> L1C_WAY_DIS_W<8> {
181 L1C_WAY_DIS_W::new(self)
182 }
183 #[doc = "Bit 12"]
184 #[inline(always)]
185 #[must_use]
186 pub fn irom_2t_access(&mut self) -> IROM_2T_ACCESS_W<12> {
187 IROM_2T_ACCESS_W::new(self)
188 }
189 #[doc = "Bit 14"]
190 #[inline(always)]
191 #[must_use]
192 pub fn l1c_bypass(&mut self) -> L1C_BYPASS_W<14> {
193 L1C_BYPASS_W::new(self)
194 }
195 #[doc = "Bit 15"]
196 #[inline(always)]
197 #[must_use]
198 pub fn l1c_bmx_err_en(&mut self) -> L1C_BMX_ERR_EN_W<15> {
199 L1C_BMX_ERR_EN_W::new(self)
200 }
201 #[doc = "Bits 16:17"]
202 #[inline(always)]
203 #[must_use]
204 pub fn l1c_bmx_arb_mode(&mut self) -> L1C_BMX_ARB_MODE_W<16> {
205 L1C_BMX_ARB_MODE_W::new(self)
206 }
207 #[doc = "Bits 20:23"]
208 #[inline(always)]
209 #[must_use]
210 pub fn l1c_bmx_timeout_en(&mut self) -> L1C_BMX_TIMEOUT_EN_W<20> {
211 L1C_BMX_TIMEOUT_EN_W::new(self)
212 }
213 #[doc = "Bit 24"]
214 #[inline(always)]
215 #[must_use]
216 pub fn l1c_bmx_busy_option_dis(&mut self) -> L1C_BMX_BUSY_OPTION_DIS_W<24> {
217 L1C_BMX_BUSY_OPTION_DIS_W::new(self)
218 }
219 #[doc = "Bit 25"]
220 #[inline(always)]
221 #[must_use]
222 pub fn early_resp_dis(&mut self) -> EARLY_RESP_DIS_W<25> {
223 EARLY_RESP_DIS_W::new(self)
224 }
225 #[doc = "Bit 26"]
226 #[inline(always)]
227 #[must_use]
228 pub fn wrap_dis(&mut self) -> WRAP_DIS_W<26> {
229 WRAP_DIS_W::new(self)
230 }
231 #[doc = "Writes raw bits to the register."]
232 #[inline(always)]
233 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
234 self.0.bits(bits);
235 self
236 }
237}
238#[doc = "l1c_config.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [l1c_config](index.html) module"]
239pub struct L1C_CONFIG_SPEC;
240impl crate::RegisterSpec for L1C_CONFIG_SPEC {
241 type Ux = u32;
242}
243#[doc = "`read()` method returns [l1c_config::R](R) reader structure"]
244impl crate::Readable for L1C_CONFIG_SPEC {
245 type Reader = R;
246}
247#[doc = "`write(|w| ..)` method takes [l1c_config::W](W) writer structure"]
248impl crate::Writable for L1C_CONFIG_SPEC {
249 type Writer = W;
250 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
251 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
252}
253#[doc = "`reset()` method sets l1c_config to value 0x0600_0f00"]
254impl crate::Resettable for L1C_CONFIG_SPEC {
255 const RESET_VALUE: Self::Ux = 0x0600_0f00;
256}