bl602_pac/l1c/
cpu_clk_gate.rs

1#[doc = "Register `cpu_clk_gate` reader"]
2pub struct R(crate::R<CPU_CLK_GATE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CPU_CLK_GATE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CPU_CLK_GATE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CPU_CLK_GATE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `cpu_clk_gate` writer"]
17pub struct W(crate::W<CPU_CLK_GATE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CPU_CLK_GATE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CPU_CLK_GATE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CPU_CLK_GATE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `force_e21_clock_on_0` reader - "]
38pub type FORCE_E21_CLOCK_ON_0_R = crate::BitReader<bool>;
39#[doc = "Field `force_e21_clock_on_0` writer - "]
40pub type FORCE_E21_CLOCK_ON_0_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, CPU_CLK_GATE_SPEC, bool, O>;
42#[doc = "Field `force_e21_clock_on_1` reader - "]
43pub type FORCE_E21_CLOCK_ON_1_R = crate::BitReader<bool>;
44#[doc = "Field `force_e21_clock_on_1` writer - "]
45pub type FORCE_E21_CLOCK_ON_1_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, CPU_CLK_GATE_SPEC, bool, O>;
47#[doc = "Field `force_e21_clock_on_2` reader - "]
48pub type FORCE_E21_CLOCK_ON_2_R = crate::BitReader<bool>;
49#[doc = "Field `force_e21_clock_on_2` writer - "]
50pub type FORCE_E21_CLOCK_ON_2_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, CPU_CLK_GATE_SPEC, bool, O>;
52impl R {
53    #[doc = "Bit 0"]
54    #[inline(always)]
55    pub fn force_e21_clock_on_0(&self) -> FORCE_E21_CLOCK_ON_0_R {
56        FORCE_E21_CLOCK_ON_0_R::new((self.bits & 1) != 0)
57    }
58    #[doc = "Bit 1"]
59    #[inline(always)]
60    pub fn force_e21_clock_on_1(&self) -> FORCE_E21_CLOCK_ON_1_R {
61        FORCE_E21_CLOCK_ON_1_R::new(((self.bits >> 1) & 1) != 0)
62    }
63    #[doc = "Bit 2"]
64    #[inline(always)]
65    pub fn force_e21_clock_on_2(&self) -> FORCE_E21_CLOCK_ON_2_R {
66        FORCE_E21_CLOCK_ON_2_R::new(((self.bits >> 2) & 1) != 0)
67    }
68}
69impl W {
70    #[doc = "Bit 0"]
71    #[inline(always)]
72    #[must_use]
73    pub fn force_e21_clock_on_0(&mut self) -> FORCE_E21_CLOCK_ON_0_W<0> {
74        FORCE_E21_CLOCK_ON_0_W::new(self)
75    }
76    #[doc = "Bit 1"]
77    #[inline(always)]
78    #[must_use]
79    pub fn force_e21_clock_on_1(&mut self) -> FORCE_E21_CLOCK_ON_1_W<1> {
80        FORCE_E21_CLOCK_ON_1_W::new(self)
81    }
82    #[doc = "Bit 2"]
83    #[inline(always)]
84    #[must_use]
85    pub fn force_e21_clock_on_2(&mut self) -> FORCE_E21_CLOCK_ON_2_W<2> {
86        FORCE_E21_CLOCK_ON_2_W::new(self)
87    }
88    #[doc = "Writes raw bits to the register."]
89    #[inline(always)]
90    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
91        self.0.bits(bits);
92        self
93    }
94}
95#[doc = "cpu_clk_gate.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu_clk_gate](index.html) module"]
96pub struct CPU_CLK_GATE_SPEC;
97impl crate::RegisterSpec for CPU_CLK_GATE_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [cpu_clk_gate::R](R) reader structure"]
101impl crate::Readable for CPU_CLK_GATE_SPEC {
102    type Reader = R;
103}
104#[doc = "`write(|w| ..)` method takes [cpu_clk_gate::W](W) writer structure"]
105impl crate::Writable for CPU_CLK_GATE_SPEC {
106    type Writer = W;
107    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109}
110#[doc = "`reset()` method sets cpu_clk_gate to value 0"]
111impl crate::Resettable for CPU_CLK_GATE_SPEC {
112    const RESET_VALUE: Self::Ux = 0;
113}
bl602_pac/l1c/cpu_clk_gate.rs

bl602_pac/l1c/
cpu_clk_gate.rs
