1#[doc = "Register `glb_parm` reader"]
2pub struct R(crate::R<GLB_PARM_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<GLB_PARM_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<GLB_PARM_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<GLB_PARM_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `glb_parm` writer"]
17pub struct W(crate::W<GLB_PARM_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<GLB_PARM_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<GLB_PARM_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<GLB_PARM_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `reg_bd_en` reader - "]
38pub type REG_BD_EN_R = crate::BitReader<bool>;
39#[doc = "Field `reg_bd_en` writer - "]
40pub type REG_BD_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
41#[doc = "Field `reg_ext_rst_smt` reader - "]
42pub type REG_EXT_RST_SMT_R = crate::BitReader<bool>;
43#[doc = "Field `reg_ext_rst_smt` writer - "]
44pub type REG_EXT_RST_SMT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
45#[doc = "Field `jtag_swap_set` reader - "]
46pub type JTAG_SWAP_SET_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `jtag_swap_set` writer - "]
48pub type JTAG_SWAP_SET_W<'a, const O: u8> =
49 crate::FieldWriter<'a, u32, GLB_PARM_SPEC, u8, u8, 6, O>;
50#[doc = "Field `swap_sflash_io_3_io_0` reader - "]
51pub type SWAP_SFLASH_IO_3_IO_0_R = crate::BitReader<bool>;
52#[doc = "Field `swap_sflash_io_3_io_0` writer - "]
53pub type SWAP_SFLASH_IO_3_IO_0_W<'a, const O: u8> =
54 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
55#[doc = "Field `sel_embedded_sflash` reader - "]
56pub type SEL_EMBEDDED_SFLASH_R = crate::BitReader<bool>;
57#[doc = "Field `sel_embedded_sflash` writer - "]
58pub type SEL_EMBEDDED_SFLASH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
59#[doc = "Field `reg_spi_0_master_mode` reader - "]
60pub type REG_SPI_0_MASTER_MODE_R = crate::BitReader<bool>;
61#[doc = "Field `reg_spi_0_master_mode` writer - "]
62pub type REG_SPI_0_MASTER_MODE_W<'a, const O: u8> =
63 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
64#[doc = "Field `reg_spi_0_swap` reader - "]
65pub type REG_SPI_0_SWAP_R = crate::BitReader<bool>;
66#[doc = "Field `reg_spi_0_swap` writer - "]
67pub type REG_SPI_0_SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
68#[doc = "Field `reg_cci_use_jtag_pin` reader - "]
69pub type REG_CCI_USE_JTAG_PIN_R = crate::BitReader<bool>;
70#[doc = "Field `reg_cci_use_jtag_pin` writer - "]
71pub type REG_CCI_USE_JTAG_PIN_W<'a, const O: u8> =
72 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
73#[doc = "Field `reg_cci_use_sdio_pin` reader - "]
74pub type REG_CCI_USE_SDIO_PIN_R = crate::BitReader<bool>;
75#[doc = "Field `reg_cci_use_sdio_pin` writer - "]
76pub type REG_CCI_USE_SDIO_PIN_W<'a, const O: u8> =
77 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
78#[doc = "Field `p1_adc_test_with_cci` reader - "]
79pub type P1_ADC_TEST_WITH_CCI_R = crate::BitReader<bool>;
80#[doc = "Field `p1_adc_test_with_cci` writer - "]
81pub type P1_ADC_TEST_WITH_CCI_W<'a, const O: u8> =
82 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
83#[doc = "Field `p2_dac_test_with_cci` reader - "]
84pub type P2_DAC_TEST_WITH_CCI_R = crate::BitReader<bool>;
85#[doc = "Field `p2_dac_test_with_cci` writer - "]
86pub type P2_DAC_TEST_WITH_CCI_W<'a, const O: u8> =
87 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
88#[doc = "Field `p3_cci_use_io_2_5` reader - "]
89pub type P3_CCI_USE_IO_2_5_R = crate::BitReader<bool>;
90#[doc = "Field `p3_cci_use_io_2_5` writer - "]
91pub type P3_CCI_USE_IO_2_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
92#[doc = "Field `p4_adc_test_with_jtag` reader - "]
93pub type P4_ADC_TEST_WITH_JTAG_R = crate::BitReader<bool>;
94#[doc = "Field `p4_adc_test_with_jtag` writer - "]
95pub type P4_ADC_TEST_WITH_JTAG_W<'a, const O: u8> =
96 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
97#[doc = "Field `p5_dac_test_with_jtag` reader - "]
98pub type P5_DAC_TEST_WITH_JTAG_R = crate::BitReader<bool>;
99#[doc = "Field `p5_dac_test_with_jtag` writer - "]
100pub type P5_DAC_TEST_WITH_JTAG_W<'a, const O: u8> =
101 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
102#[doc = "Field `p6_sdio_use_io_0_5` reader - "]
103pub type P6_SDIO_USE_IO_0_5_R = crate::BitReader<bool>;
104#[doc = "Field `p6_sdio_use_io_0_5` writer - "]
105pub type P6_SDIO_USE_IO_0_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
106#[doc = "Field `p7_jtag_use_io_2_5` reader - "]
107pub type P7_JTAG_USE_IO_2_5_R = crate::BitReader<bool>;
108#[doc = "Field `p7_jtag_use_io_2_5` writer - "]
109pub type P7_JTAG_USE_IO_2_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
110#[doc = "Field `uart_swap_set` reader - "]
111pub type UART_SWAP_SET_R = crate::FieldReader<u8, u8>;
112#[doc = "Field `uart_swap_set` writer - "]
113pub type UART_SWAP_SET_W<'a, const O: u8> =
114 crate::FieldWriter<'a, u32, GLB_PARM_SPEC, u8, u8, 3, O>;
115impl R {
116 #[doc = "Bit 0"]
117 #[inline(always)]
118 pub fn reg_bd_en(&self) -> REG_BD_EN_R {
119 REG_BD_EN_R::new((self.bits & 1) != 0)
120 }
121 #[doc = "Bit 1"]
122 #[inline(always)]
123 pub fn reg_ext_rst_smt(&self) -> REG_EXT_RST_SMT_R {
124 REG_EXT_RST_SMT_R::new(((self.bits >> 1) & 1) != 0)
125 }
126 #[doc = "Bits 2:7"]
127 #[inline(always)]
128 pub fn jtag_swap_set(&self) -> JTAG_SWAP_SET_R {
129 JTAG_SWAP_SET_R::new(((self.bits >> 2) & 0x3f) as u8)
130 }
131 #[doc = "Bit 8"]
132 #[inline(always)]
133 pub fn swap_sflash_io_3_io_0(&self) -> SWAP_SFLASH_IO_3_IO_0_R {
134 SWAP_SFLASH_IO_3_IO_0_R::new(((self.bits >> 8) & 1) != 0)
135 }
136 #[doc = "Bit 9"]
137 #[inline(always)]
138 pub fn sel_embedded_sflash(&self) -> SEL_EMBEDDED_SFLASH_R {
139 SEL_EMBEDDED_SFLASH_R::new(((self.bits >> 9) & 1) != 0)
140 }
141 #[doc = "Bit 12"]
142 #[inline(always)]
143 pub fn reg_spi_0_master_mode(&self) -> REG_SPI_0_MASTER_MODE_R {
144 REG_SPI_0_MASTER_MODE_R::new(((self.bits >> 12) & 1) != 0)
145 }
146 #[doc = "Bit 13"]
147 #[inline(always)]
148 pub fn reg_spi_0_swap(&self) -> REG_SPI_0_SWAP_R {
149 REG_SPI_0_SWAP_R::new(((self.bits >> 13) & 1) != 0)
150 }
151 #[doc = "Bit 15"]
152 #[inline(always)]
153 pub fn reg_cci_use_jtag_pin(&self) -> REG_CCI_USE_JTAG_PIN_R {
154 REG_CCI_USE_JTAG_PIN_R::new(((self.bits >> 15) & 1) != 0)
155 }
156 #[doc = "Bit 16"]
157 #[inline(always)]
158 pub fn reg_cci_use_sdio_pin(&self) -> REG_CCI_USE_SDIO_PIN_R {
159 REG_CCI_USE_SDIO_PIN_R::new(((self.bits >> 16) & 1) != 0)
160 }
161 #[doc = "Bit 17"]
162 #[inline(always)]
163 pub fn p1_adc_test_with_cci(&self) -> P1_ADC_TEST_WITH_CCI_R {
164 P1_ADC_TEST_WITH_CCI_R::new(((self.bits >> 17) & 1) != 0)
165 }
166 #[doc = "Bit 18"]
167 #[inline(always)]
168 pub fn p2_dac_test_with_cci(&self) -> P2_DAC_TEST_WITH_CCI_R {
169 P2_DAC_TEST_WITH_CCI_R::new(((self.bits >> 18) & 1) != 0)
170 }
171 #[doc = "Bit 19"]
172 #[inline(always)]
173 pub fn p3_cci_use_io_2_5(&self) -> P3_CCI_USE_IO_2_5_R {
174 P3_CCI_USE_IO_2_5_R::new(((self.bits >> 19) & 1) != 0)
175 }
176 #[doc = "Bit 20"]
177 #[inline(always)]
178 pub fn p4_adc_test_with_jtag(&self) -> P4_ADC_TEST_WITH_JTAG_R {
179 P4_ADC_TEST_WITH_JTAG_R::new(((self.bits >> 20) & 1) != 0)
180 }
181 #[doc = "Bit 21"]
182 #[inline(always)]
183 pub fn p5_dac_test_with_jtag(&self) -> P5_DAC_TEST_WITH_JTAG_R {
184 P5_DAC_TEST_WITH_JTAG_R::new(((self.bits >> 21) & 1) != 0)
185 }
186 #[doc = "Bit 22"]
187 #[inline(always)]
188 pub fn p6_sdio_use_io_0_5(&self) -> P6_SDIO_USE_IO_0_5_R {
189 P6_SDIO_USE_IO_0_5_R::new(((self.bits >> 22) & 1) != 0)
190 }
191 #[doc = "Bit 23"]
192 #[inline(always)]
193 pub fn p7_jtag_use_io_2_5(&self) -> P7_JTAG_USE_IO_2_5_R {
194 P7_JTAG_USE_IO_2_5_R::new(((self.bits >> 23) & 1) != 0)
195 }
196 #[doc = "Bits 24:26"]
197 #[inline(always)]
198 pub fn uart_swap_set(&self) -> UART_SWAP_SET_R {
199 UART_SWAP_SET_R::new(((self.bits >> 24) & 7) as u8)
200 }
201}
202impl W {
203 #[doc = "Bit 0"]
204 #[inline(always)]
205 #[must_use]
206 pub fn reg_bd_en(&mut self) -> REG_BD_EN_W<0> {
207 REG_BD_EN_W::new(self)
208 }
209 #[doc = "Bit 1"]
210 #[inline(always)]
211 #[must_use]
212 pub fn reg_ext_rst_smt(&mut self) -> REG_EXT_RST_SMT_W<1> {
213 REG_EXT_RST_SMT_W::new(self)
214 }
215 #[doc = "Bits 2:7"]
216 #[inline(always)]
217 #[must_use]
218 pub fn jtag_swap_set(&mut self) -> JTAG_SWAP_SET_W<2> {
219 JTAG_SWAP_SET_W::new(self)
220 }
221 #[doc = "Bit 8"]
222 #[inline(always)]
223 #[must_use]
224 pub fn swap_sflash_io_3_io_0(&mut self) -> SWAP_SFLASH_IO_3_IO_0_W<8> {
225 SWAP_SFLASH_IO_3_IO_0_W::new(self)
226 }
227 #[doc = "Bit 9"]
228 #[inline(always)]
229 #[must_use]
230 pub fn sel_embedded_sflash(&mut self) -> SEL_EMBEDDED_SFLASH_W<9> {
231 SEL_EMBEDDED_SFLASH_W::new(self)
232 }
233 #[doc = "Bit 12"]
234 #[inline(always)]
235 #[must_use]
236 pub fn reg_spi_0_master_mode(&mut self) -> REG_SPI_0_MASTER_MODE_W<12> {
237 REG_SPI_0_MASTER_MODE_W::new(self)
238 }
239 #[doc = "Bit 13"]
240 #[inline(always)]
241 #[must_use]
242 pub fn reg_spi_0_swap(&mut self) -> REG_SPI_0_SWAP_W<13> {
243 REG_SPI_0_SWAP_W::new(self)
244 }
245 #[doc = "Bit 15"]
246 #[inline(always)]
247 #[must_use]
248 pub fn reg_cci_use_jtag_pin(&mut self) -> REG_CCI_USE_JTAG_PIN_W<15> {
249 REG_CCI_USE_JTAG_PIN_W::new(self)
250 }
251 #[doc = "Bit 16"]
252 #[inline(always)]
253 #[must_use]
254 pub fn reg_cci_use_sdio_pin(&mut self) -> REG_CCI_USE_SDIO_PIN_W<16> {
255 REG_CCI_USE_SDIO_PIN_W::new(self)
256 }
257 #[doc = "Bit 17"]
258 #[inline(always)]
259 #[must_use]
260 pub fn p1_adc_test_with_cci(&mut self) -> P1_ADC_TEST_WITH_CCI_W<17> {
261 P1_ADC_TEST_WITH_CCI_W::new(self)
262 }
263 #[doc = "Bit 18"]
264 #[inline(always)]
265 #[must_use]
266 pub fn p2_dac_test_with_cci(&mut self) -> P2_DAC_TEST_WITH_CCI_W<18> {
267 P2_DAC_TEST_WITH_CCI_W::new(self)
268 }
269 #[doc = "Bit 19"]
270 #[inline(always)]
271 #[must_use]
272 pub fn p3_cci_use_io_2_5(&mut self) -> P3_CCI_USE_IO_2_5_W<19> {
273 P3_CCI_USE_IO_2_5_W::new(self)
274 }
275 #[doc = "Bit 20"]
276 #[inline(always)]
277 #[must_use]
278 pub fn p4_adc_test_with_jtag(&mut self) -> P4_ADC_TEST_WITH_JTAG_W<20> {
279 P4_ADC_TEST_WITH_JTAG_W::new(self)
280 }
281 #[doc = "Bit 21"]
282 #[inline(always)]
283 #[must_use]
284 pub fn p5_dac_test_with_jtag(&mut self) -> P5_DAC_TEST_WITH_JTAG_W<21> {
285 P5_DAC_TEST_WITH_JTAG_W::new(self)
286 }
287 #[doc = "Bit 22"]
288 #[inline(always)]
289 #[must_use]
290 pub fn p6_sdio_use_io_0_5(&mut self) -> P6_SDIO_USE_IO_0_5_W<22> {
291 P6_SDIO_USE_IO_0_5_W::new(self)
292 }
293 #[doc = "Bit 23"]
294 #[inline(always)]
295 #[must_use]
296 pub fn p7_jtag_use_io_2_5(&mut self) -> P7_JTAG_USE_IO_2_5_W<23> {
297 P7_JTAG_USE_IO_2_5_W::new(self)
298 }
299 #[doc = "Bits 24:26"]
300 #[inline(always)]
301 #[must_use]
302 pub fn uart_swap_set(&mut self) -> UART_SWAP_SET_W<24> {
303 UART_SWAP_SET_W::new(self)
304 }
305 #[doc = "Writes raw bits to the register."]
306 #[inline(always)]
307 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
308 self.0.bits(bits);
309 self
310 }
311}
312#[doc = "glb_parm.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [glb_parm](index.html) module"]
313pub struct GLB_PARM_SPEC;
314impl crate::RegisterSpec for GLB_PARM_SPEC {
315 type Ux = u32;
316}
317#[doc = "`read()` method returns [glb_parm::R](R) reader structure"]
318impl crate::Readable for GLB_PARM_SPEC {
319 type Reader = R;
320}
321#[doc = "`write(|w| ..)` method takes [glb_parm::W](W) writer structure"]
322impl crate::Writable for GLB_PARM_SPEC {
323 type Writer = W;
324 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
325 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
326}
327#[doc = "`reset()` method sets glb_parm to value 0x0001_8300"]
328impl crate::Resettable for GLB_PARM_SPEC {
329 const RESET_VALUE: Self::Ux = 0x0001_8300;
330}