bl602_pac/l1c/
l1c_bmx_err_addr_en.rs1#[doc = "Register `l1c_bmx_err_addr_en` reader"]
2pub struct R(crate::R<L1C_BMX_ERR_ADDR_EN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<L1C_BMX_ERR_ADDR_EN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<L1C_BMX_ERR_ADDR_EN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<L1C_BMX_ERR_ADDR_EN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `l1c_bmx_err_addr_en` writer"]
17pub struct W(crate::W<L1C_BMX_ERR_ADDR_EN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<L1C_BMX_ERR_ADDR_EN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<L1C_BMX_ERR_ADDR_EN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<L1C_BMX_ERR_ADDR_EN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `l1c_bmx_err_addr_dis` reader - "]
38pub type L1C_BMX_ERR_ADDR_DIS_R = crate::BitReader<bool>;
39#[doc = "Field `l1c_bmx_err_addr_dis` writer - "]
40pub type L1C_BMX_ERR_ADDR_DIS_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, L1C_BMX_ERR_ADDR_EN_SPEC, bool, O>;
42#[doc = "Field `l1c_bmx_err_dec` reader - "]
43pub type L1C_BMX_ERR_DEC_R = crate::BitReader<bool>;
44#[doc = "Field `l1c_bmx_err_tz` reader - "]
45pub type L1C_BMX_ERR_TZ_R = crate::BitReader<bool>;
46#[doc = "Field `l1c_hsel_option` reader - "]
47pub type L1C_HSEL_OPTION_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `l1c_hsel_option` writer - "]
49pub type L1C_HSEL_OPTION_W<'a, const O: u8> =
50 crate::FieldWriter<'a, u32, L1C_BMX_ERR_ADDR_EN_SPEC, u8, u8, 4, O>;
51impl R {
52 #[doc = "Bit 0"]
53 #[inline(always)]
54 pub fn l1c_bmx_err_addr_dis(&self) -> L1C_BMX_ERR_ADDR_DIS_R {
55 L1C_BMX_ERR_ADDR_DIS_R::new((self.bits & 1) != 0)
56 }
57 #[doc = "Bit 4"]
58 #[inline(always)]
59 pub fn l1c_bmx_err_dec(&self) -> L1C_BMX_ERR_DEC_R {
60 L1C_BMX_ERR_DEC_R::new(((self.bits >> 4) & 1) != 0)
61 }
62 #[doc = "Bit 5"]
63 #[inline(always)]
64 pub fn l1c_bmx_err_tz(&self) -> L1C_BMX_ERR_TZ_R {
65 L1C_BMX_ERR_TZ_R::new(((self.bits >> 5) & 1) != 0)
66 }
67 #[doc = "Bits 16:19"]
68 #[inline(always)]
69 pub fn l1c_hsel_option(&self) -> L1C_HSEL_OPTION_R {
70 L1C_HSEL_OPTION_R::new(((self.bits >> 16) & 0x0f) as u8)
71 }
72}
73impl W {
74 #[doc = "Bit 0"]
75 #[inline(always)]
76 #[must_use]
77 pub fn l1c_bmx_err_addr_dis(&mut self) -> L1C_BMX_ERR_ADDR_DIS_W<0> {
78 L1C_BMX_ERR_ADDR_DIS_W::new(self)
79 }
80 #[doc = "Bits 16:19"]
81 #[inline(always)]
82 #[must_use]
83 pub fn l1c_hsel_option(&mut self) -> L1C_HSEL_OPTION_W<16> {
84 L1C_HSEL_OPTION_W::new(self)
85 }
86 #[doc = "Writes raw bits to the register."]
87 #[inline(always)]
88 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89 self.0.bits(bits);
90 self
91 }
92}
93#[doc = "l1c_bmx_err_addr_en.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [l1c_bmx_err_addr_en](index.html) module"]
94pub struct L1C_BMX_ERR_ADDR_EN_SPEC;
95impl crate::RegisterSpec for L1C_BMX_ERR_ADDR_EN_SPEC {
96 type Ux = u32;
97}
98#[doc = "`read()` method returns [l1c_bmx_err_addr_en::R](R) reader structure"]
99impl crate::Readable for L1C_BMX_ERR_ADDR_EN_SPEC {
100 type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [l1c_bmx_err_addr_en::W](W) writer structure"]
103impl crate::Writable for L1C_BMX_ERR_ADDR_EN_SPEC {
104 type Writer = W;
105 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107}
108#[doc = "`reset()` method sets l1c_bmx_err_addr_en to value 0"]
109impl crate::Resettable for L1C_BMX_ERR_ADDR_EN_SPEC {
110 const RESET_VALUE: Self::Ux = 0;
111}