bl602_pac/ir/
irrx_swm_fifo_config_0.rs

1#[doc = "Register `irrx_swm_fifo_config_0` reader"]
2pub struct R(crate::R<IRRX_SWM_FIFO_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IRRX_SWM_FIFO_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IRRX_SWM_FIFO_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IRRX_SWM_FIFO_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `irrx_swm_fifo_config_0` writer"]
17pub struct W(crate::W<IRRX_SWM_FIFO_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IRRX_SWM_FIFO_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IRRX_SWM_FIFO_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IRRX_SWM_FIFO_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `rx_fifo_clr` reader - "]
38pub type RX_FIFO_CLR_R = crate::BitReader<bool>;
39#[doc = "Field `rx_fifo_clr` writer - "]
40pub type RX_FIFO_CLR_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, IRRX_SWM_FIFO_CONFIG_0_SPEC, bool, O>;
42#[doc = "Field `rx_fifo_overflow` reader - "]
43pub type RX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
44#[doc = "Field `rx_fifo_underflow` reader - "]
45pub type RX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
46#[doc = "Field `rx_fifo_cnt` reader - "]
47pub type RX_FIFO_CNT_R = crate::FieldReader<u8, u8>;
48impl R {
49    #[doc = "Bit 0"]
50    #[inline(always)]
51    pub fn rx_fifo_clr(&self) -> RX_FIFO_CLR_R {
52        RX_FIFO_CLR_R::new((self.bits & 1) != 0)
53    }
54    #[doc = "Bit 2"]
55    #[inline(always)]
56    pub fn rx_fifo_overflow(&self) -> RX_FIFO_OVERFLOW_R {
57        RX_FIFO_OVERFLOW_R::new(((self.bits >> 2) & 1) != 0)
58    }
59    #[doc = "Bit 3"]
60    #[inline(always)]
61    pub fn rx_fifo_underflow(&self) -> RX_FIFO_UNDERFLOW_R {
62        RX_FIFO_UNDERFLOW_R::new(((self.bits >> 3) & 1) != 0)
63    }
64    #[doc = "Bits 4:10"]
65    #[inline(always)]
66    pub fn rx_fifo_cnt(&self) -> RX_FIFO_CNT_R {
67        RX_FIFO_CNT_R::new(((self.bits >> 4) & 0x7f) as u8)
68    }
69}
70impl W {
71    #[doc = "Bit 0"]
72    #[inline(always)]
73    #[must_use]
74    pub fn rx_fifo_clr(&mut self) -> RX_FIFO_CLR_W<0> {
75        RX_FIFO_CLR_W::new(self)
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "irrx_swm_fifo_config_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irrx_swm_fifo_config_0](index.html) module"]
85pub struct IRRX_SWM_FIFO_CONFIG_0_SPEC;
86impl crate::RegisterSpec for IRRX_SWM_FIFO_CONFIG_0_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [irrx_swm_fifo_config_0::R](R) reader structure"]
90impl crate::Readable for IRRX_SWM_FIFO_CONFIG_0_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [irrx_swm_fifo_config_0::W](W) writer structure"]
94impl crate::Writable for IRRX_SWM_FIFO_CONFIG_0_SPEC {
95    type Writer = W;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
98}
99#[doc = "`reset()` method sets irrx_swm_fifo_config_0 to value 0"]
100impl crate::Resettable for IRRX_SWM_FIFO_CONFIG_0_SPEC {
101    const RESET_VALUE: Self::Ux = 0;
102}
bl602_pac/ir/irrx_swm_fifo_config_0.rs

bl602_pac/ir/
irrx_swm_fifo_config_0.rs
