bl602_pac/glb/
clk_cfg2.rs1#[doc = "Register `clk_cfg2` reader"]
2pub struct R(crate::R<CLK_CFG2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLK_CFG2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLK_CFG2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLK_CFG2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `clk_cfg2` writer"]
17pub struct W(crate::W<CLK_CFG2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLK_CFG2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLK_CFG2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLK_CFG2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `uart_clk_div` reader - "]
38pub type UART_CLK_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `uart_clk_div` writer - "]
40pub type UART_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 3, O>;
41#[doc = "Field `uart_clk_en` reader - "]
42pub type UART_CLK_EN_R = crate::BitReader<bool>;
43#[doc = "Field `uart_clk_en` writer - "]
44pub type UART_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
45#[doc = "Field `hbn_uart_clk_sel` reader - "]
46pub type HBN_UART_CLK_SEL_R = crate::BitReader<bool>;
47#[doc = "Field `sf_clk_div` reader - "]
48pub type SF_CLK_DIV_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `sf_clk_div` writer - "]
50pub type SF_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 3, O>;
51#[doc = "Field `sf_clk_en` reader - "]
52pub type SF_CLK_EN_R = crate::BitReader<bool>;
53#[doc = "Field `sf_clk_en` writer - "]
54pub type SF_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
55#[doc = "Field `sf_clk_sel` reader - "]
56pub type SF_CLK_SEL_R = crate::FieldReader<u8, u8>;
57#[doc = "Field `sf_clk_sel` writer - "]
58pub type SF_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 2, O>;
59#[doc = "Field `sf_clk_sel2` reader - "]
60pub type SF_CLK_SEL2_R = crate::FieldReader<u8, u8>;
61#[doc = "Field `sf_clk_sel2` writer - "]
62pub type SF_CLK_SEL2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 2, O>;
63#[doc = "Field `ir_clk_div` reader - "]
64pub type IR_CLK_DIV_R = crate::FieldReader<u8, u8>;
65#[doc = "Field `ir_clk_div` writer - "]
66pub type IR_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 6, O>;
67#[doc = "Field `ir_clk_en` reader - "]
68pub type IR_CLK_EN_R = crate::BitReader<bool>;
69#[doc = "Field `ir_clk_en` writer - "]
70pub type IR_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
71#[doc = "Field `dma_clk_en` reader - "]
72pub type DMA_CLK_EN_R = crate::FieldReader<u8, u8>;
73#[doc = "Field `dma_clk_en` writer - "]
74pub type DMA_CLK_EN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 8, O>;
75impl R {
76 #[doc = "Bits 0:2"]
77 #[inline(always)]
78 pub fn uart_clk_div(&self) -> UART_CLK_DIV_R {
79 UART_CLK_DIV_R::new((self.bits & 7) as u8)
80 }
81 #[doc = "Bit 4"]
82 #[inline(always)]
83 pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
84 UART_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
85 }
86 #[doc = "Bit 7"]
87 #[inline(always)]
88 pub fn hbn_uart_clk_sel(&self) -> HBN_UART_CLK_SEL_R {
89 HBN_UART_CLK_SEL_R::new(((self.bits >> 7) & 1) != 0)
90 }
91 #[doc = "Bits 8:10"]
92 #[inline(always)]
93 pub fn sf_clk_div(&self) -> SF_CLK_DIV_R {
94 SF_CLK_DIV_R::new(((self.bits >> 8) & 7) as u8)
95 }
96 #[doc = "Bit 11"]
97 #[inline(always)]
98 pub fn sf_clk_en(&self) -> SF_CLK_EN_R {
99 SF_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
100 }
101 #[doc = "Bits 12:13"]
102 #[inline(always)]
103 pub fn sf_clk_sel(&self) -> SF_CLK_SEL_R {
104 SF_CLK_SEL_R::new(((self.bits >> 12) & 3) as u8)
105 }
106 #[doc = "Bits 14:15"]
107 #[inline(always)]
108 pub fn sf_clk_sel2(&self) -> SF_CLK_SEL2_R {
109 SF_CLK_SEL2_R::new(((self.bits >> 14) & 3) as u8)
110 }
111 #[doc = "Bits 16:21"]
112 #[inline(always)]
113 pub fn ir_clk_div(&self) -> IR_CLK_DIV_R {
114 IR_CLK_DIV_R::new(((self.bits >> 16) & 0x3f) as u8)
115 }
116 #[doc = "Bit 23"]
117 #[inline(always)]
118 pub fn ir_clk_en(&self) -> IR_CLK_EN_R {
119 IR_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
120 }
121 #[doc = "Bits 24:31"]
122 #[inline(always)]
123 pub fn dma_clk_en(&self) -> DMA_CLK_EN_R {
124 DMA_CLK_EN_R::new(((self.bits >> 24) & 0xff) as u8)
125 }
126}
127impl W {
128 #[doc = "Bits 0:2"]
129 #[inline(always)]
130 #[must_use]
131 pub fn uart_clk_div(&mut self) -> UART_CLK_DIV_W<0> {
132 UART_CLK_DIV_W::new(self)
133 }
134 #[doc = "Bit 4"]
135 #[inline(always)]
136 #[must_use]
137 pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<4> {
138 UART_CLK_EN_W::new(self)
139 }
140 #[doc = "Bits 8:10"]
141 #[inline(always)]
142 #[must_use]
143 pub fn sf_clk_div(&mut self) -> SF_CLK_DIV_W<8> {
144 SF_CLK_DIV_W::new(self)
145 }
146 #[doc = "Bit 11"]
147 #[inline(always)]
148 #[must_use]
149 pub fn sf_clk_en(&mut self) -> SF_CLK_EN_W<11> {
150 SF_CLK_EN_W::new(self)
151 }
152 #[doc = "Bits 12:13"]
153 #[inline(always)]
154 #[must_use]
155 pub fn sf_clk_sel(&mut self) -> SF_CLK_SEL_W<12> {
156 SF_CLK_SEL_W::new(self)
157 }
158 #[doc = "Bits 14:15"]
159 #[inline(always)]
160 #[must_use]
161 pub fn sf_clk_sel2(&mut self) -> SF_CLK_SEL2_W<14> {
162 SF_CLK_SEL2_W::new(self)
163 }
164 #[doc = "Bits 16:21"]
165 #[inline(always)]
166 #[must_use]
167 pub fn ir_clk_div(&mut self) -> IR_CLK_DIV_W<16> {
168 IR_CLK_DIV_W::new(self)
169 }
170 #[doc = "Bit 23"]
171 #[inline(always)]
172 #[must_use]
173 pub fn ir_clk_en(&mut self) -> IR_CLK_EN_W<23> {
174 IR_CLK_EN_W::new(self)
175 }
176 #[doc = "Bits 24:31"]
177 #[inline(always)]
178 #[must_use]
179 pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<24> {
180 DMA_CLK_EN_W::new(self)
181 }
182 #[doc = "Writes raw bits to the register."]
183 #[inline(always)]
184 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
185 self.0.bits(bits);
186 self
187 }
188}
189#[doc = "Clock configuration for UART and Flash\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg2](index.html) module"]
190pub struct CLK_CFG2_SPEC;
191impl crate::RegisterSpec for CLK_CFG2_SPEC {
192 type Ux = u32;
193}
194#[doc = "`read()` method returns [clk_cfg2::R](R) reader structure"]
195impl crate::Readable for CLK_CFG2_SPEC {
196 type Reader = R;
197}
198#[doc = "`write(|w| ..)` method takes [clk_cfg2::W](W) writer structure"]
199impl crate::Writable for CLK_CFG2_SPEC {
200 type Writer = W;
201 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
202 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
203}
204#[doc = "`reset()` method sets clk_cfg2 to value 0xff8f_2b17"]
205impl crate::Resettable for CLK_CFG2_SPEC {
206 const RESET_VALUE: Self::Ux = 0xff8f_2b17;
207}