bl602_pac/aon/
dcdc18_top_0.rs1#[doc = "Register `dcdc18_top_0` reader"]
2pub struct R(crate::R<DCDC18_TOP_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DCDC18_TOP_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DCDC18_TOP_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DCDC18_TOP_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `dcdc18_top_0` writer"]
17pub struct W(crate::W<DCDC18_TOP_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DCDC18_TOP_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DCDC18_TOP_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DCDC18_TOP_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `dcdc18_vout_sel_aon` reader - "]
38pub type DCDC18_VOUT_SEL_AON_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `dcdc18_vout_sel_aon` writer - "]
40pub type DCDC18_VOUT_SEL_AON_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 5, O>;
42#[doc = "Field `dcdc18_vpfm_aon` reader - "]
43pub type DCDC18_VPFM_AON_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `dcdc18_vpfm_aon` writer - "]
45pub type DCDC18_VPFM_AON_W<'a, const O: u8> =
46 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 4, O>;
47#[doc = "Field `dcdc18_osc_2m_mode_aon` reader - "]
48pub type DCDC18_OSC_2M_MODE_AON_R = crate::BitReader<bool>;
49#[doc = "Field `dcdc18_osc_2m_mode_aon` writer - "]
50pub type DCDC18_OSC_2M_MODE_AON_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
52#[doc = "Field `dcdc18_osc_freq_trim_aon` reader - "]
53pub type DCDC18_OSC_FREQ_TRIM_AON_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `dcdc18_osc_freq_trim_aon` writer - "]
55pub type DCDC18_OSC_FREQ_TRIM_AON_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 4, O>;
57#[doc = "Field `dcdc18_slope_curr_sel_aon` reader - "]
58pub type DCDC18_SLOPE_CURR_SEL_AON_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `dcdc18_slope_curr_sel_aon` writer - "]
60pub type DCDC18_SLOPE_CURR_SEL_AON_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 5, O>;
62#[doc = "Field `dcdc18_stop_osc_aon` reader - "]
63pub type DCDC18_STOP_OSC_AON_R = crate::BitReader<bool>;
64#[doc = "Field `dcdc18_stop_osc_aon` writer - "]
65pub type DCDC18_STOP_OSC_AON_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
67#[doc = "Field `dcdc18_slow_osc_aon` reader - "]
68pub type DCDC18_SLOW_OSC_AON_R = crate::BitReader<bool>;
69#[doc = "Field `dcdc18_slow_osc_aon` writer - "]
70pub type DCDC18_SLOW_OSC_AON_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
72#[doc = "Field `dcdc18_osc_inhibit_t2_aon` reader - "]
73pub type DCDC18_OSC_INHIBIT_T2_AON_R = crate::BitReader<bool>;
74#[doc = "Field `dcdc18_osc_inhibit_t2_aon` writer - "]
75pub type DCDC18_OSC_INHIBIT_T2_AON_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
77#[doc = "Field `dcdc18_sstart_time_aon` reader - "]
78pub type DCDC18_SSTART_TIME_AON_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `dcdc18_sstart_time_aon` writer - "]
80pub type DCDC18_SSTART_TIME_AON_W<'a, const O: u8> =
81 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 2, O>;
82#[doc = "Field `dcdc18_rdy_aon` reader - "]
83pub type DCDC18_RDY_AON_R = crate::BitReader<bool>;
84impl R {
85 #[doc = "Bits 1:5"]
86 #[inline(always)]
87 pub fn dcdc18_vout_sel_aon(&self) -> DCDC18_VOUT_SEL_AON_R {
88 DCDC18_VOUT_SEL_AON_R::new(((self.bits >> 1) & 0x1f) as u8)
89 }
90 #[doc = "Bits 8:11"]
91 #[inline(always)]
92 pub fn dcdc18_vpfm_aon(&self) -> DCDC18_VPFM_AON_R {
93 DCDC18_VPFM_AON_R::new(((self.bits >> 8) & 0x0f) as u8)
94 }
95 #[doc = "Bit 12"]
96 #[inline(always)]
97 pub fn dcdc18_osc_2m_mode_aon(&self) -> DCDC18_OSC_2M_MODE_AON_R {
98 DCDC18_OSC_2M_MODE_AON_R::new(((self.bits >> 12) & 1) != 0)
99 }
100 #[doc = "Bits 16:19"]
101 #[inline(always)]
102 pub fn dcdc18_osc_freq_trim_aon(&self) -> DCDC18_OSC_FREQ_TRIM_AON_R {
103 DCDC18_OSC_FREQ_TRIM_AON_R::new(((self.bits >> 16) & 0x0f) as u8)
104 }
105 #[doc = "Bits 20:24"]
106 #[inline(always)]
107 pub fn dcdc18_slope_curr_sel_aon(&self) -> DCDC18_SLOPE_CURR_SEL_AON_R {
108 DCDC18_SLOPE_CURR_SEL_AON_R::new(((self.bits >> 20) & 0x1f) as u8)
109 }
110 #[doc = "Bit 25"]
111 #[inline(always)]
112 pub fn dcdc18_stop_osc_aon(&self) -> DCDC18_STOP_OSC_AON_R {
113 DCDC18_STOP_OSC_AON_R::new(((self.bits >> 25) & 1) != 0)
114 }
115 #[doc = "Bit 26"]
116 #[inline(always)]
117 pub fn dcdc18_slow_osc_aon(&self) -> DCDC18_SLOW_OSC_AON_R {
118 DCDC18_SLOW_OSC_AON_R::new(((self.bits >> 26) & 1) != 0)
119 }
120 #[doc = "Bit 27"]
121 #[inline(always)]
122 pub fn dcdc18_osc_inhibit_t2_aon(&self) -> DCDC18_OSC_INHIBIT_T2_AON_R {
123 DCDC18_OSC_INHIBIT_T2_AON_R::new(((self.bits >> 27) & 1) != 0)
124 }
125 #[doc = "Bits 28:29"]
126 #[inline(always)]
127 pub fn dcdc18_sstart_time_aon(&self) -> DCDC18_SSTART_TIME_AON_R {
128 DCDC18_SSTART_TIME_AON_R::new(((self.bits >> 28) & 3) as u8)
129 }
130 #[doc = "Bit 31"]
131 #[inline(always)]
132 pub fn dcdc18_rdy_aon(&self) -> DCDC18_RDY_AON_R {
133 DCDC18_RDY_AON_R::new(((self.bits >> 31) & 1) != 0)
134 }
135}
136impl W {
137 #[doc = "Bits 1:5"]
138 #[inline(always)]
139 #[must_use]
140 pub fn dcdc18_vout_sel_aon(&mut self) -> DCDC18_VOUT_SEL_AON_W<1> {
141 DCDC18_VOUT_SEL_AON_W::new(self)
142 }
143 #[doc = "Bits 8:11"]
144 #[inline(always)]
145 #[must_use]
146 pub fn dcdc18_vpfm_aon(&mut self) -> DCDC18_VPFM_AON_W<8> {
147 DCDC18_VPFM_AON_W::new(self)
148 }
149 #[doc = "Bit 12"]
150 #[inline(always)]
151 #[must_use]
152 pub fn dcdc18_osc_2m_mode_aon(&mut self) -> DCDC18_OSC_2M_MODE_AON_W<12> {
153 DCDC18_OSC_2M_MODE_AON_W::new(self)
154 }
155 #[doc = "Bits 16:19"]
156 #[inline(always)]
157 #[must_use]
158 pub fn dcdc18_osc_freq_trim_aon(&mut self) -> DCDC18_OSC_FREQ_TRIM_AON_W<16> {
159 DCDC18_OSC_FREQ_TRIM_AON_W::new(self)
160 }
161 #[doc = "Bits 20:24"]
162 #[inline(always)]
163 #[must_use]
164 pub fn dcdc18_slope_curr_sel_aon(&mut self) -> DCDC18_SLOPE_CURR_SEL_AON_W<20> {
165 DCDC18_SLOPE_CURR_SEL_AON_W::new(self)
166 }
167 #[doc = "Bit 25"]
168 #[inline(always)]
169 #[must_use]
170 pub fn dcdc18_stop_osc_aon(&mut self) -> DCDC18_STOP_OSC_AON_W<25> {
171 DCDC18_STOP_OSC_AON_W::new(self)
172 }
173 #[doc = "Bit 26"]
174 #[inline(always)]
175 #[must_use]
176 pub fn dcdc18_slow_osc_aon(&mut self) -> DCDC18_SLOW_OSC_AON_W<26> {
177 DCDC18_SLOW_OSC_AON_W::new(self)
178 }
179 #[doc = "Bit 27"]
180 #[inline(always)]
181 #[must_use]
182 pub fn dcdc18_osc_inhibit_t2_aon(&mut self) -> DCDC18_OSC_INHIBIT_T2_AON_W<27> {
183 DCDC18_OSC_INHIBIT_T2_AON_W::new(self)
184 }
185 #[doc = "Bits 28:29"]
186 #[inline(always)]
187 #[must_use]
188 pub fn dcdc18_sstart_time_aon(&mut self) -> DCDC18_SSTART_TIME_AON_W<28> {
189 DCDC18_SSTART_TIME_AON_W::new(self)
190 }
191 #[doc = "Writes raw bits to the register."]
192 #[inline(always)]
193 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
194 self.0.bits(bits);
195 self
196 }
197}
198#[doc = "dcdc18_top_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdc18_top_0](index.html) module"]
199pub struct DCDC18_TOP_0_SPEC;
200impl crate::RegisterSpec for DCDC18_TOP_0_SPEC {
201 type Ux = u32;
202}
203#[doc = "`read()` method returns [dcdc18_top_0::R](R) reader structure"]
204impl crate::Readable for DCDC18_TOP_0_SPEC {
205 type Reader = R;
206}
207#[doc = "`write(|w| ..)` method takes [dcdc18_top_0::W](W) writer structure"]
208impl crate::Writable for DCDC18_TOP_0_SPEC {
209 type Writer = W;
210 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
211 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
212}
213#[doc = "`reset()` method sets dcdc18_top_0 to value 0x8a58_0736"]
214impl crate::Resettable for DCDC18_TOP_0_SPEC {
215 const RESET_VALUE: Self::Ux = 0x8a58_0736;
216}