bl602_pac/uart/
uart_int_sts.rs

1#[doc = "Register `uart_int_sts` reader"]
2pub struct R(crate::R<UART_INT_STS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_INT_STS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_INT_STS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_INT_STS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `utx_end_int` reader - "]
17pub type UTX_END_INT_R = crate::BitReader<bool>;
18#[doc = "Field `urx_end_int` reader - "]
19pub type URX_END_INT_R = crate::BitReader<bool>;
20#[doc = "Field `utx_fifo_int` reader - "]
21pub type UTX_FIFO_INT_R = crate::BitReader<bool>;
22#[doc = "Field `urx_fifo_int` reader - "]
23pub type URX_FIFO_INT_R = crate::BitReader<bool>;
24#[doc = "Field `urx_rto_int` reader - "]
25pub type URX_RTO_INT_R = crate::BitReader<bool>;
26#[doc = "Field `urx_pce_int` reader - "]
27pub type URX_PCE_INT_R = crate::BitReader<bool>;
28#[doc = "Field `utx_fer_int` reader - "]
29pub type UTX_FER_INT_R = crate::BitReader<bool>;
30#[doc = "Field `urx_fer_int` reader - "]
31pub type URX_FER_INT_R = crate::BitReader<bool>;
32impl R {
33    #[doc = "Bit 0"]
34    #[inline(always)]
35    pub fn utx_end_int(&self) -> UTX_END_INT_R {
36        UTX_END_INT_R::new((self.bits & 1) != 0)
37    }
38    #[doc = "Bit 1"]
39    #[inline(always)]
40    pub fn urx_end_int(&self) -> URX_END_INT_R {
41        URX_END_INT_R::new(((self.bits >> 1) & 1) != 0)
42    }
43    #[doc = "Bit 2"]
44    #[inline(always)]
45    pub fn utx_fifo_int(&self) -> UTX_FIFO_INT_R {
46        UTX_FIFO_INT_R::new(((self.bits >> 2) & 1) != 0)
47    }
48    #[doc = "Bit 3"]
49    #[inline(always)]
50    pub fn urx_fifo_int(&self) -> URX_FIFO_INT_R {
51        URX_FIFO_INT_R::new(((self.bits >> 3) & 1) != 0)
52    }
53    #[doc = "Bit 4"]
54    #[inline(always)]
55    pub fn urx_rto_int(&self) -> URX_RTO_INT_R {
56        URX_RTO_INT_R::new(((self.bits >> 4) & 1) != 0)
57    }
58    #[doc = "Bit 5"]
59    #[inline(always)]
60    pub fn urx_pce_int(&self) -> URX_PCE_INT_R {
61        URX_PCE_INT_R::new(((self.bits >> 5) & 1) != 0)
62    }
63    #[doc = "Bit 6"]
64    #[inline(always)]
65    pub fn utx_fer_int(&self) -> UTX_FER_INT_R {
66        UTX_FER_INT_R::new(((self.bits >> 6) & 1) != 0)
67    }
68    #[doc = "Bit 7"]
69    #[inline(always)]
70    pub fn urx_fer_int(&self) -> URX_FER_INT_R {
71        URX_FER_INT_R::new(((self.bits >> 7) & 1) != 0)
72    }
73}
74#[doc = "UART interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_sts](index.html) module"]
75pub struct UART_INT_STS_SPEC;
76impl crate::RegisterSpec for UART_INT_STS_SPEC {
77    type Ux = u32;
78}
79#[doc = "`read()` method returns [uart_int_sts::R](R) reader structure"]
80impl crate::Readable for UART_INT_STS_SPEC {
81    type Reader = R;
82}
83#[doc = "`reset()` method sets uart_int_sts to value 0"]
84impl crate::Resettable for UART_INT_STS_SPEC {
85    const RESET_VALUE: Self::Ux = 0;
86}
bl602_pac/uart/uart_int_sts.rs

bl602_pac/uart/
uart_int_sts.rs
