bl602_pac/uart/
uart_int_clear.rs

1#[doc = "Register `uart_int_clear` reader"]
2pub struct R(crate::R<UART_INT_CLEAR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_INT_CLEAR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_INT_CLEAR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_INT_CLEAR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_int_clear` writer"]
17pub struct W(crate::W<UART_INT_CLEAR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_INT_CLEAR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_INT_CLEAR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_INT_CLEAR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cr_utx_end_clr` reader - "]
38pub type CR_UTX_END_CLR_R = crate::BitReader<bool>;
39#[doc = "Field `cr_utx_end_clr` writer - "]
40pub type CR_UTX_END_CLR_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
42#[doc = "Field `cr_urx_end_clr` reader - "]
43pub type CR_URX_END_CLR_R = crate::BitReader<bool>;
44#[doc = "Field `cr_urx_end_clr` writer - "]
45pub type CR_URX_END_CLR_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
47#[doc = "Field `rsvd_2` reader - "]
48pub type RSVD_2_R = crate::BitReader<bool>;
49#[doc = "Field `rsvd_2` writer - "]
50pub type RSVD_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
51#[doc = "Field `rsvd_3` reader - "]
52pub type RSVD_3_R = crate::BitReader<bool>;
53#[doc = "Field `rsvd_3` writer - "]
54pub type RSVD_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
55#[doc = "Field `cr_urx_rto_clr` reader - "]
56pub type CR_URX_RTO_CLR_R = crate::BitReader<bool>;
57#[doc = "Field `cr_urx_rto_clr` writer - "]
58pub type CR_URX_RTO_CLR_W<'a, const O: u8> =
59    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
60#[doc = "Field `cr_urx_pce_clr` reader - "]
61pub type CR_URX_PCE_CLR_R = crate::BitReader<bool>;
62#[doc = "Field `cr_urx_pce_clr` writer - "]
63pub type CR_URX_PCE_CLR_W<'a, const O: u8> =
64    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
65#[doc = "Field `rsvd_6` reader - "]
66pub type RSVD_6_R = crate::BitReader<bool>;
67#[doc = "Field `rsvd_6` writer - "]
68pub type RSVD_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
69#[doc = "Field `rsvd_7` reader - "]
70pub type RSVD_7_R = crate::BitReader<bool>;
71#[doc = "Field `rsvd_7` writer - "]
72pub type RSVD_7_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
73impl R {
74    #[doc = "Bit 0"]
75    #[inline(always)]
76    pub fn cr_utx_end_clr(&self) -> CR_UTX_END_CLR_R {
77        CR_UTX_END_CLR_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1"]
80    #[inline(always)]
81    pub fn cr_urx_end_clr(&self) -> CR_URX_END_CLR_R {
82        CR_URX_END_CLR_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2"]
85    #[inline(always)]
86    pub fn rsvd_2(&self) -> RSVD_2_R {
87        RSVD_2_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3"]
90    #[inline(always)]
91    pub fn rsvd_3(&self) -> RSVD_3_R {
92        RSVD_3_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4"]
95    #[inline(always)]
96    pub fn cr_urx_rto_clr(&self) -> CR_URX_RTO_CLR_R {
97        CR_URX_RTO_CLR_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 5"]
100    #[inline(always)]
101    pub fn cr_urx_pce_clr(&self) -> CR_URX_PCE_CLR_R {
102        CR_URX_PCE_CLR_R::new(((self.bits >> 5) & 1) != 0)
103    }
104    #[doc = "Bit 6"]
105    #[inline(always)]
106    pub fn rsvd_6(&self) -> RSVD_6_R {
107        RSVD_6_R::new(((self.bits >> 6) & 1) != 0)
108    }
109    #[doc = "Bit 7"]
110    #[inline(always)]
111    pub fn rsvd_7(&self) -> RSVD_7_R {
112        RSVD_7_R::new(((self.bits >> 7) & 1) != 0)
113    }
114}
115impl W {
116    #[doc = "Bit 0"]
117    #[inline(always)]
118    #[must_use]
119    pub fn cr_utx_end_clr(&mut self) -> CR_UTX_END_CLR_W<0> {
120        CR_UTX_END_CLR_W::new(self)
121    }
122    #[doc = "Bit 1"]
123    #[inline(always)]
124    #[must_use]
125    pub fn cr_urx_end_clr(&mut self) -> CR_URX_END_CLR_W<1> {
126        CR_URX_END_CLR_W::new(self)
127    }
128    #[doc = "Bit 2"]
129    #[inline(always)]
130    #[must_use]
131    pub fn rsvd_2(&mut self) -> RSVD_2_W<2> {
132        RSVD_2_W::new(self)
133    }
134    #[doc = "Bit 3"]
135    #[inline(always)]
136    #[must_use]
137    pub fn rsvd_3(&mut self) -> RSVD_3_W<3> {
138        RSVD_3_W::new(self)
139    }
140    #[doc = "Bit 4"]
141    #[inline(always)]
142    #[must_use]
143    pub fn cr_urx_rto_clr(&mut self) -> CR_URX_RTO_CLR_W<4> {
144        CR_URX_RTO_CLR_W::new(self)
145    }
146    #[doc = "Bit 5"]
147    #[inline(always)]
148    #[must_use]
149    pub fn cr_urx_pce_clr(&mut self) -> CR_URX_PCE_CLR_W<5> {
150        CR_URX_PCE_CLR_W::new(self)
151    }
152    #[doc = "Bit 6"]
153    #[inline(always)]
154    #[must_use]
155    pub fn rsvd_6(&mut self) -> RSVD_6_W<6> {
156        RSVD_6_W::new(self)
157    }
158    #[doc = "Bit 7"]
159    #[inline(always)]
160    #[must_use]
161    pub fn rsvd_7(&mut self) -> RSVD_7_W<7> {
162        RSVD_7_W::new(self)
163    }
164    #[doc = "Writes raw bits to the register."]
165    #[inline(always)]
166    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
167        self.0.bits(bits);
168        self
169    }
170}
171#[doc = "UART interrupt clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_clear](index.html) module"]
172pub struct UART_INT_CLEAR_SPEC;
173impl crate::RegisterSpec for UART_INT_CLEAR_SPEC {
174    type Ux = u32;
175}
176#[doc = "`read()` method returns [uart_int_clear::R](R) reader structure"]
177impl crate::Readable for UART_INT_CLEAR_SPEC {
178    type Reader = R;
179}
180#[doc = "`write(|w| ..)` method takes [uart_int_clear::W](W) writer structure"]
181impl crate::Writable for UART_INT_CLEAR_SPEC {
182    type Writer = W;
183    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
184    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
185}
186#[doc = "`reset()` method sets uart_int_clear to value 0"]
187impl crate::Resettable for UART_INT_CLEAR_SPEC {
188    const RESET_VALUE: Self::Ux = 0;
189}
bl602_pac/uart/uart_int_clear.rs

bl602_pac/uart/
uart_int_clear.rs
