bl602_pac/spi/
spi_fifo_config_1.rs

1#[doc = "Register `spi_fifo_config_1` reader"]
2pub struct R(crate::R<SPI_FIFO_CONFIG_1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPI_FIFO_CONFIG_1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPI_FIFO_CONFIG_1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPI_FIFO_CONFIG_1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `spi_fifo_config_1` writer"]
17pub struct W(crate::W<SPI_FIFO_CONFIG_1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPI_FIFO_CONFIG_1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPI_FIFO_CONFIG_1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPI_FIFO_CONFIG_1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `tx_fifo_cnt` reader - "]
38pub type TX_FIFO_CNT_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `rx_fifo_cnt` reader - "]
40pub type RX_FIFO_CNT_R = crate::FieldReader<u8, u8>;
41#[doc = "Field `tx_fifo_th` reader - "]
42pub type TX_FIFO_TH_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `tx_fifo_th` writer - "]
44pub type TX_FIFO_TH_W<'a, const O: u8> =
45    crate::FieldWriter<'a, u32, SPI_FIFO_CONFIG_1_SPEC, u8, u8, 2, O>;
46#[doc = "Field `rx_fifo_th` reader - "]
47pub type RX_FIFO_TH_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `rx_fifo_th` writer - "]
49pub type RX_FIFO_TH_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, SPI_FIFO_CONFIG_1_SPEC, u8, u8, 2, O>;
51impl R {
52    #[doc = "Bits 0:2"]
53    #[inline(always)]
54    pub fn tx_fifo_cnt(&self) -> TX_FIFO_CNT_R {
55        TX_FIFO_CNT_R::new((self.bits & 7) as u8)
56    }
57    #[doc = "Bits 8:10"]
58    #[inline(always)]
59    pub fn rx_fifo_cnt(&self) -> RX_FIFO_CNT_R {
60        RX_FIFO_CNT_R::new(((self.bits >> 8) & 7) as u8)
61    }
62    #[doc = "Bits 16:17"]
63    #[inline(always)]
64    pub fn tx_fifo_th(&self) -> TX_FIFO_TH_R {
65        TX_FIFO_TH_R::new(((self.bits >> 16) & 3) as u8)
66    }
67    #[doc = "Bits 24:25"]
68    #[inline(always)]
69    pub fn rx_fifo_th(&self) -> RX_FIFO_TH_R {
70        RX_FIFO_TH_R::new(((self.bits >> 24) & 3) as u8)
71    }
72}
73impl W {
74    #[doc = "Bits 16:17"]
75    #[inline(always)]
76    #[must_use]
77    pub fn tx_fifo_th(&mut self) -> TX_FIFO_TH_W<16> {
78        TX_FIFO_TH_W::new(self)
79    }
80    #[doc = "Bits 24:25"]
81    #[inline(always)]
82    #[must_use]
83    pub fn rx_fifo_th(&mut self) -> RX_FIFO_TH_W<24> {
84        RX_FIFO_TH_W::new(self)
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "spi_fifo_config_1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_fifo_config_1](index.html) module"]
94pub struct SPI_FIFO_CONFIG_1_SPEC;
95impl crate::RegisterSpec for SPI_FIFO_CONFIG_1_SPEC {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [spi_fifo_config_1::R](R) reader structure"]
99impl crate::Readable for SPI_FIFO_CONFIG_1_SPEC {
100    type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [spi_fifo_config_1::W](W) writer structure"]
103impl crate::Writable for SPI_FIFO_CONFIG_1_SPEC {
104    type Writer = W;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107}
108#[doc = "`reset()` method sets spi_fifo_config_1 to value 0x04"]
109impl crate::Resettable for SPI_FIFO_CONFIG_1_SPEC {
110    const RESET_VALUE: Self::Ux = 0x04;
111}
bl602_pac/spi/spi_fifo_config_1.rs

bl602_pac/spi/
spi_fifo_config_1.rs
