bl602_pac/sec_eng/
se_gmac_0_ctrl_0.rs1#[doc = "Register `se_gmac_0_ctrl_0` reader"]
2pub struct R(crate::R<SE_GMAC_0_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SE_GMAC_0_CTRL_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SE_GMAC_0_CTRL_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SE_GMAC_0_CTRL_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `se_gmac_0_ctrl_0` writer"]
17pub struct W(crate::W<SE_GMAC_0_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SE_GMAC_0_CTRL_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SE_GMAC_0_CTRL_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SE_GMAC_0_CTRL_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `se_gmac_0_busy` reader - "]
38pub type SE_GMAC_0_BUSY_R = crate::BitReader<bool>;
39#[doc = "Field `se_gmac_0_trig_1t` reader - "]
40pub type SE_GMAC_0_TRIG_1T_R = crate::BitReader<bool>;
41#[doc = "Field `se_gmac_0_trig_1t` writer - "]
42pub type SE_GMAC_0_TRIG_1T_W<'a, const O: u8> =
43 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
44#[doc = "Field `se_gmac_0_en` reader - "]
45pub type SE_GMAC_0_EN_R = crate::BitReader<bool>;
46#[doc = "Field `se_gmac_0_en` writer - "]
47pub type SE_GMAC_0_EN_W<'a, const O: u8> =
48 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
49#[doc = "Field `se_gmac_0_int` reader - "]
50pub type SE_GMAC_0_INT_R = crate::BitReader<bool>;
51#[doc = "Field `se_gmac_0_int_clr_1t` reader - "]
52pub type SE_GMAC_0_INT_CLR_1T_R = crate::BitReader<bool>;
53#[doc = "Field `se_gmac_0_int_clr_1t` writer - "]
54pub type SE_GMAC_0_INT_CLR_1T_W<'a, const O: u8> =
55 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
56#[doc = "Field `se_gmac_0_int_set_1t` reader - "]
57pub type SE_GMAC_0_INT_SET_1T_R = crate::BitReader<bool>;
58#[doc = "Field `se_gmac_0_int_set_1t` writer - "]
59pub type SE_GMAC_0_INT_SET_1T_W<'a, const O: u8> =
60 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
61#[doc = "Field `se_gmac_0_int_mask` reader - "]
62pub type SE_GMAC_0_INT_MASK_R = crate::BitReader<bool>;
63#[doc = "Field `se_gmac_0_int_mask` writer - "]
64pub type SE_GMAC_0_INT_MASK_W<'a, const O: u8> =
65 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
66#[doc = "Field `se_gmac_0_t_endian` reader - "]
67pub type SE_GMAC_0_T_ENDIAN_R = crate::BitReader<bool>;
68#[doc = "Field `se_gmac_0_t_endian` writer - "]
69pub type SE_GMAC_0_T_ENDIAN_W<'a, const O: u8> =
70 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
71#[doc = "Field `se_gmac_0_h_endian` reader - "]
72pub type SE_GMAC_0_H_ENDIAN_R = crate::BitReader<bool>;
73#[doc = "Field `se_gmac_0_h_endian` writer - "]
74pub type SE_GMAC_0_H_ENDIAN_W<'a, const O: u8> =
75 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
76#[doc = "Field `se_gmac_0_x_endian` reader - "]
77pub type SE_GMAC_0_X_ENDIAN_R = crate::BitReader<bool>;
78#[doc = "Field `se_gmac_0_x_endian` writer - "]
79pub type SE_GMAC_0_X_ENDIAN_W<'a, const O: u8> =
80 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
81impl R {
82 #[doc = "Bit 0"]
83 #[inline(always)]
84 pub fn se_gmac_0_busy(&self) -> SE_GMAC_0_BUSY_R {
85 SE_GMAC_0_BUSY_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 1"]
88 #[inline(always)]
89 pub fn se_gmac_0_trig_1t(&self) -> SE_GMAC_0_TRIG_1T_R {
90 SE_GMAC_0_TRIG_1T_R::new(((self.bits >> 1) & 1) != 0)
91 }
92 #[doc = "Bit 2"]
93 #[inline(always)]
94 pub fn se_gmac_0_en(&self) -> SE_GMAC_0_EN_R {
95 SE_GMAC_0_EN_R::new(((self.bits >> 2) & 1) != 0)
96 }
97 #[doc = "Bit 8"]
98 #[inline(always)]
99 pub fn se_gmac_0_int(&self) -> SE_GMAC_0_INT_R {
100 SE_GMAC_0_INT_R::new(((self.bits >> 8) & 1) != 0)
101 }
102 #[doc = "Bit 9"]
103 #[inline(always)]
104 pub fn se_gmac_0_int_clr_1t(&self) -> SE_GMAC_0_INT_CLR_1T_R {
105 SE_GMAC_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
106 }
107 #[doc = "Bit 10"]
108 #[inline(always)]
109 pub fn se_gmac_0_int_set_1t(&self) -> SE_GMAC_0_INT_SET_1T_R {
110 SE_GMAC_0_INT_SET_1T_R::new(((self.bits >> 10) & 1) != 0)
111 }
112 #[doc = "Bit 11"]
113 #[inline(always)]
114 pub fn se_gmac_0_int_mask(&self) -> SE_GMAC_0_INT_MASK_R {
115 SE_GMAC_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
116 }
117 #[doc = "Bit 12"]
118 #[inline(always)]
119 pub fn se_gmac_0_t_endian(&self) -> SE_GMAC_0_T_ENDIAN_R {
120 SE_GMAC_0_T_ENDIAN_R::new(((self.bits >> 12) & 1) != 0)
121 }
122 #[doc = "Bit 13"]
123 #[inline(always)]
124 pub fn se_gmac_0_h_endian(&self) -> SE_GMAC_0_H_ENDIAN_R {
125 SE_GMAC_0_H_ENDIAN_R::new(((self.bits >> 13) & 1) != 0)
126 }
127 #[doc = "Bit 14"]
128 #[inline(always)]
129 pub fn se_gmac_0_x_endian(&self) -> SE_GMAC_0_X_ENDIAN_R {
130 SE_GMAC_0_X_ENDIAN_R::new(((self.bits >> 14) & 1) != 0)
131 }
132}
133impl W {
134 #[doc = "Bit 1"]
135 #[inline(always)]
136 #[must_use]
137 pub fn se_gmac_0_trig_1t(&mut self) -> SE_GMAC_0_TRIG_1T_W<1> {
138 SE_GMAC_0_TRIG_1T_W::new(self)
139 }
140 #[doc = "Bit 2"]
141 #[inline(always)]
142 #[must_use]
143 pub fn se_gmac_0_en(&mut self) -> SE_GMAC_0_EN_W<2> {
144 SE_GMAC_0_EN_W::new(self)
145 }
146 #[doc = "Bit 9"]
147 #[inline(always)]
148 #[must_use]
149 pub fn se_gmac_0_int_clr_1t(&mut self) -> SE_GMAC_0_INT_CLR_1T_W<9> {
150 SE_GMAC_0_INT_CLR_1T_W::new(self)
151 }
152 #[doc = "Bit 10"]
153 #[inline(always)]
154 #[must_use]
155 pub fn se_gmac_0_int_set_1t(&mut self) -> SE_GMAC_0_INT_SET_1T_W<10> {
156 SE_GMAC_0_INT_SET_1T_W::new(self)
157 }
158 #[doc = "Bit 11"]
159 #[inline(always)]
160 #[must_use]
161 pub fn se_gmac_0_int_mask(&mut self) -> SE_GMAC_0_INT_MASK_W<11> {
162 SE_GMAC_0_INT_MASK_W::new(self)
163 }
164 #[doc = "Bit 12"]
165 #[inline(always)]
166 #[must_use]
167 pub fn se_gmac_0_t_endian(&mut self) -> SE_GMAC_0_T_ENDIAN_W<12> {
168 SE_GMAC_0_T_ENDIAN_W::new(self)
169 }
170 #[doc = "Bit 13"]
171 #[inline(always)]
172 #[must_use]
173 pub fn se_gmac_0_h_endian(&mut self) -> SE_GMAC_0_H_ENDIAN_W<13> {
174 SE_GMAC_0_H_ENDIAN_W::new(self)
175 }
176 #[doc = "Bit 14"]
177 #[inline(always)]
178 #[must_use]
179 pub fn se_gmac_0_x_endian(&mut self) -> SE_GMAC_0_X_ENDIAN_W<14> {
180 SE_GMAC_0_X_ENDIAN_W::new(self)
181 }
182 #[doc = "Writes raw bits to the register."]
183 #[inline(always)]
184 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
185 self.0.bits(bits);
186 self
187 }
188}
189#[doc = "se_gmac_0_ctrl_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_gmac_0_ctrl_0](index.html) module"]
190pub struct SE_GMAC_0_CTRL_0_SPEC;
191impl crate::RegisterSpec for SE_GMAC_0_CTRL_0_SPEC {
192 type Ux = u32;
193}
194#[doc = "`read()` method returns [se_gmac_0_ctrl_0::R](R) reader structure"]
195impl crate::Readable for SE_GMAC_0_CTRL_0_SPEC {
196 type Reader = R;
197}
198#[doc = "`write(|w| ..)` method takes [se_gmac_0_ctrl_0::W](W) writer structure"]
199impl crate::Writable for SE_GMAC_0_CTRL_0_SPEC {
200 type Writer = W;
201 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
202 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
203}
204#[doc = "`reset()` method sets se_gmac_0_ctrl_0 to value 0x7000"]
205impl crate::Resettable for SE_GMAC_0_CTRL_0_SPEC {
206 const RESET_VALUE: Self::Ux = 0x7000;
207}