bl602_pac/rf/
rf_sram_ctrl1.rs

1#[doc = "Register `rf_sram_ctrl1` reader"]
2pub struct R(crate::R<RF_SRAM_CTRL1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RF_SRAM_CTRL1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RF_SRAM_CTRL1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RF_SRAM_CTRL1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `rf_sram_ctrl1` writer"]
17pub struct W(crate::W<RF_SRAM_CTRL1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RF_SRAM_CTRL1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RF_SRAM_CTRL1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RF_SRAM_CTRL1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `rf_sram_adc_done` reader - "]
38pub type RF_SRAM_ADC_DONE_R = crate::BitReader<bool>;
39#[doc = "Field `rf_sram_adc_done` writer - "]
40pub type RF_SRAM_ADC_DONE_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, RF_SRAM_CTRL1_SPEC, bool, O>;
42#[doc = "Field `rf_sram_adc_en` reader - "]
43pub type RF_SRAM_ADC_EN_R = crate::BitReader<bool>;
44#[doc = "Field `rf_sram_adc_en` writer - "]
45pub type RF_SRAM_ADC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, RF_SRAM_CTRL1_SPEC, bool, O>;
46#[doc = "Field `rf_sram_adc_loop_en` reader - "]
47pub type RF_SRAM_ADC_LOOP_EN_R = crate::BitReader<bool>;
48#[doc = "Field `rf_sram_adc_loop_en` writer - "]
49pub type RF_SRAM_ADC_LOOP_EN_W<'a, const O: u8> =
50    crate::BitWriter<'a, u32, RF_SRAM_CTRL1_SPEC, bool, O>;
51#[doc = "Field `rf_sram_adc_sts_clr` reader - "]
52pub type RF_SRAM_ADC_STS_CLR_R = crate::BitReader<bool>;
53#[doc = "Field `rf_sram_adc_sts_clr` writer - "]
54pub type RF_SRAM_ADC_STS_CLR_W<'a, const O: u8> =
55    crate::BitWriter<'a, u32, RF_SRAM_CTRL1_SPEC, bool, O>;
56#[doc = "Field `rf_sram_adc_done_cnt` reader - "]
57pub type RF_SRAM_ADC_DONE_CNT_R = crate::FieldReader<u16, u16>;
58#[doc = "Field `rf_sram_adc_done_cnt` writer - "]
59pub type RF_SRAM_ADC_DONE_CNT_W<'a, const O: u8> =
60    crate::FieldWriter<'a, u32, RF_SRAM_CTRL1_SPEC, u16, u16, 16, O>;
61impl R {
62    #[doc = "Bit 0"]
63    #[inline(always)]
64    pub fn rf_sram_adc_done(&self) -> RF_SRAM_ADC_DONE_R {
65        RF_SRAM_ADC_DONE_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1"]
68    #[inline(always)]
69    pub fn rf_sram_adc_en(&self) -> RF_SRAM_ADC_EN_R {
70        RF_SRAM_ADC_EN_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2"]
73    #[inline(always)]
74    pub fn rf_sram_adc_loop_en(&self) -> RF_SRAM_ADC_LOOP_EN_R {
75        RF_SRAM_ADC_LOOP_EN_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3"]
78    #[inline(always)]
79    pub fn rf_sram_adc_sts_clr(&self) -> RF_SRAM_ADC_STS_CLR_R {
80        RF_SRAM_ADC_STS_CLR_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bits 16:31"]
83    #[inline(always)]
84    pub fn rf_sram_adc_done_cnt(&self) -> RF_SRAM_ADC_DONE_CNT_R {
85        RF_SRAM_ADC_DONE_CNT_R::new(((self.bits >> 16) & 0xffff) as u16)
86    }
87}
88impl W {
89    #[doc = "Bit 0"]
90    #[inline(always)]
91    #[must_use]
92    pub fn rf_sram_adc_done(&mut self) -> RF_SRAM_ADC_DONE_W<0> {
93        RF_SRAM_ADC_DONE_W::new(self)
94    }
95    #[doc = "Bit 1"]
96    #[inline(always)]
97    #[must_use]
98    pub fn rf_sram_adc_en(&mut self) -> RF_SRAM_ADC_EN_W<1> {
99        RF_SRAM_ADC_EN_W::new(self)
100    }
101    #[doc = "Bit 2"]
102    #[inline(always)]
103    #[must_use]
104    pub fn rf_sram_adc_loop_en(&mut self) -> RF_SRAM_ADC_LOOP_EN_W<2> {
105        RF_SRAM_ADC_LOOP_EN_W::new(self)
106    }
107    #[doc = "Bit 3"]
108    #[inline(always)]
109    #[must_use]
110    pub fn rf_sram_adc_sts_clr(&mut self) -> RF_SRAM_ADC_STS_CLR_W<3> {
111        RF_SRAM_ADC_STS_CLR_W::new(self)
112    }
113    #[doc = "Bits 16:31"]
114    #[inline(always)]
115    #[must_use]
116    pub fn rf_sram_adc_done_cnt(&mut self) -> RF_SRAM_ADC_DONE_CNT_W<16> {
117        RF_SRAM_ADC_DONE_CNT_W::new(self)
118    }
119    #[doc = "Writes raw bits to the register."]
120    #[inline(always)]
121    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
122        self.0.bits(bits);
123        self
124    }
125}
126#[doc = "rf_sram_ctrl1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rf_sram_ctrl1](index.html) module"]
127pub struct RF_SRAM_CTRL1_SPEC;
128impl crate::RegisterSpec for RF_SRAM_CTRL1_SPEC {
129    type Ux = u32;
130}
131#[doc = "`read()` method returns [rf_sram_ctrl1::R](R) reader structure"]
132impl crate::Readable for RF_SRAM_CTRL1_SPEC {
133    type Reader = R;
134}
135#[doc = "`write(|w| ..)` method takes [rf_sram_ctrl1::W](W) writer structure"]
136impl crate::Writable for RF_SRAM_CTRL1_SPEC {
137    type Writer = W;
138    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
139    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
140}
141#[doc = "`reset()` method sets rf_sram_ctrl1 to value 0"]
142impl crate::Resettable for RF_SRAM_CTRL1_SPEC {
143    const RESET_VALUE: Self::Ux = 0;
144}
bl602_pac/rf/rf_sram_ctrl1.rs

bl602_pac/rf/
rf_sram_ctrl1.rs
