bl602_pac/pds/
pds_ctl4.rs

1#[doc = "Register `PDS_CTL4` reader"]
2pub struct R(crate::R<PDS_CTL4_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDS_CTL4_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDS_CTL4_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDS_CTL4_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDS_CTL4` writer"]
17pub struct W(crate::W<PDS_CTL4_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDS_CTL4_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDS_CTL4_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDS_CTL4_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cr_pds_np_pwr_off` reader - "]
38pub type CR_PDS_NP_PWR_OFF_R = crate::BitReader<bool>;
39#[doc = "Field `cr_pds_np_pwr_off` writer - "]
40pub type CR_PDS_NP_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
41#[doc = "Field `cr_pds_np_reset` reader - "]
42pub type CR_PDS_NP_RESET_R = crate::BitReader<bool>;
43#[doc = "Field `cr_pds_np_reset` writer - "]
44pub type CR_PDS_NP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
45#[doc = "Field `cr_pds_np_mem_stby` reader - "]
46pub type CR_PDS_NP_MEM_STBY_R = crate::BitReader<bool>;
47#[doc = "Field `cr_pds_np_mem_stby` writer - "]
48pub type CR_PDS_NP_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
49#[doc = "Field `cr_pds_np_gate_clk` reader - "]
50pub type CR_PDS_NP_GATE_CLK_R = crate::BitReader<bool>;
51#[doc = "Field `cr_pds_np_gate_clk` writer - "]
52pub type CR_PDS_NP_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
53#[doc = "Field `cr_pds_wb_pwr_off` reader - "]
54pub type CR_PDS_WB_PWR_OFF_R = crate::BitReader<bool>;
55#[doc = "Field `cr_pds_wb_pwr_off` writer - "]
56pub type CR_PDS_WB_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
57#[doc = "Field `cr_pds_wb_reset` reader - "]
58pub type CR_PDS_WB_RESET_R = crate::BitReader<bool>;
59#[doc = "Field `cr_pds_wb_reset` writer - "]
60pub type CR_PDS_WB_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
61#[doc = "Field `cr_pds_wb_mem_stby` reader - "]
62pub type CR_PDS_WB_MEM_STBY_R = crate::BitReader<bool>;
63#[doc = "Field `cr_pds_wb_mem_stby` writer - "]
64pub type CR_PDS_WB_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
65#[doc = "Field `cr_pds_wb_gate_clk` reader - "]
66pub type CR_PDS_WB_GATE_CLK_R = crate::BitReader<bool>;
67#[doc = "Field `cr_pds_wb_gate_clk` writer - "]
68pub type CR_PDS_WB_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
69#[doc = "Field `cr_pds_misc_pwr_off` reader - "]
70pub type CR_PDS_MISC_PWR_OFF_R = crate::BitReader<bool>;
71#[doc = "Field `cr_pds_misc_pwr_off` writer - "]
72pub type CR_PDS_MISC_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
73#[doc = "Field `cr_pds_misc_reset` reader - "]
74pub type CR_PDS_MISC_RESET_R = crate::BitReader<bool>;
75#[doc = "Field `cr_pds_misc_reset` writer - "]
76pub type CR_PDS_MISC_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
77#[doc = "Field `cr_pds_misc_mem_stby` reader - "]
78pub type CR_PDS_MISC_MEM_STBY_R = crate::BitReader<bool>;
79#[doc = "Field `cr_pds_misc_mem_stby` writer - "]
80pub type CR_PDS_MISC_MEM_STBY_W<'a, const O: u8> =
81    crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
82#[doc = "Field `cr_pds_misc_gate_clk` reader - "]
83pub type CR_PDS_MISC_GATE_CLK_R = crate::BitReader<bool>;
84#[doc = "Field `cr_pds_misc_gate_clk` writer - "]
85pub type CR_PDS_MISC_GATE_CLK_W<'a, const O: u8> =
86    crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
87impl R {
88    #[doc = "Bit 0"]
89    #[inline(always)]
90    pub fn cr_pds_np_pwr_off(&self) -> CR_PDS_NP_PWR_OFF_R {
91        CR_PDS_NP_PWR_OFF_R::new((self.bits & 1) != 0)
92    }
93    #[doc = "Bit 1"]
94    #[inline(always)]
95    pub fn cr_pds_np_reset(&self) -> CR_PDS_NP_RESET_R {
96        CR_PDS_NP_RESET_R::new(((self.bits >> 1) & 1) != 0)
97    }
98    #[doc = "Bit 2"]
99    #[inline(always)]
100    pub fn cr_pds_np_mem_stby(&self) -> CR_PDS_NP_MEM_STBY_R {
101        CR_PDS_NP_MEM_STBY_R::new(((self.bits >> 2) & 1) != 0)
102    }
103    #[doc = "Bit 3"]
104    #[inline(always)]
105    pub fn cr_pds_np_gate_clk(&self) -> CR_PDS_NP_GATE_CLK_R {
106        CR_PDS_NP_GATE_CLK_R::new(((self.bits >> 3) & 1) != 0)
107    }
108    #[doc = "Bit 12"]
109    #[inline(always)]
110    pub fn cr_pds_wb_pwr_off(&self) -> CR_PDS_WB_PWR_OFF_R {
111        CR_PDS_WB_PWR_OFF_R::new(((self.bits >> 12) & 1) != 0)
112    }
113    #[doc = "Bit 13"]
114    #[inline(always)]
115    pub fn cr_pds_wb_reset(&self) -> CR_PDS_WB_RESET_R {
116        CR_PDS_WB_RESET_R::new(((self.bits >> 13) & 1) != 0)
117    }
118    #[doc = "Bit 14"]
119    #[inline(always)]
120    pub fn cr_pds_wb_mem_stby(&self) -> CR_PDS_WB_MEM_STBY_R {
121        CR_PDS_WB_MEM_STBY_R::new(((self.bits >> 14) & 1) != 0)
122    }
123    #[doc = "Bit 15"]
124    #[inline(always)]
125    pub fn cr_pds_wb_gate_clk(&self) -> CR_PDS_WB_GATE_CLK_R {
126        CR_PDS_WB_GATE_CLK_R::new(((self.bits >> 15) & 1) != 0)
127    }
128    #[doc = "Bit 24"]
129    #[inline(always)]
130    pub fn cr_pds_misc_pwr_off(&self) -> CR_PDS_MISC_PWR_OFF_R {
131        CR_PDS_MISC_PWR_OFF_R::new(((self.bits >> 24) & 1) != 0)
132    }
133    #[doc = "Bit 25"]
134    #[inline(always)]
135    pub fn cr_pds_misc_reset(&self) -> CR_PDS_MISC_RESET_R {
136        CR_PDS_MISC_RESET_R::new(((self.bits >> 25) & 1) != 0)
137    }
138    #[doc = "Bit 26"]
139    #[inline(always)]
140    pub fn cr_pds_misc_mem_stby(&self) -> CR_PDS_MISC_MEM_STBY_R {
141        CR_PDS_MISC_MEM_STBY_R::new(((self.bits >> 26) & 1) != 0)
142    }
143    #[doc = "Bit 27"]
144    #[inline(always)]
145    pub fn cr_pds_misc_gate_clk(&self) -> CR_PDS_MISC_GATE_CLK_R {
146        CR_PDS_MISC_GATE_CLK_R::new(((self.bits >> 27) & 1) != 0)
147    }
148}
149impl W {
150    #[doc = "Bit 0"]
151    #[inline(always)]
152    #[must_use]
153    pub fn cr_pds_np_pwr_off(&mut self) -> CR_PDS_NP_PWR_OFF_W<0> {
154        CR_PDS_NP_PWR_OFF_W::new(self)
155    }
156    #[doc = "Bit 1"]
157    #[inline(always)]
158    #[must_use]
159    pub fn cr_pds_np_reset(&mut self) -> CR_PDS_NP_RESET_W<1> {
160        CR_PDS_NP_RESET_W::new(self)
161    }
162    #[doc = "Bit 2"]
163    #[inline(always)]
164    #[must_use]
165    pub fn cr_pds_np_mem_stby(&mut self) -> CR_PDS_NP_MEM_STBY_W<2> {
166        CR_PDS_NP_MEM_STBY_W::new(self)
167    }
168    #[doc = "Bit 3"]
169    #[inline(always)]
170    #[must_use]
171    pub fn cr_pds_np_gate_clk(&mut self) -> CR_PDS_NP_GATE_CLK_W<3> {
172        CR_PDS_NP_GATE_CLK_W::new(self)
173    }
174    #[doc = "Bit 12"]
175    #[inline(always)]
176    #[must_use]
177    pub fn cr_pds_wb_pwr_off(&mut self) -> CR_PDS_WB_PWR_OFF_W<12> {
178        CR_PDS_WB_PWR_OFF_W::new(self)
179    }
180    #[doc = "Bit 13"]
181    #[inline(always)]
182    #[must_use]
183    pub fn cr_pds_wb_reset(&mut self) -> CR_PDS_WB_RESET_W<13> {
184        CR_PDS_WB_RESET_W::new(self)
185    }
186    #[doc = "Bit 14"]
187    #[inline(always)]
188    #[must_use]
189    pub fn cr_pds_wb_mem_stby(&mut self) -> CR_PDS_WB_MEM_STBY_W<14> {
190        CR_PDS_WB_MEM_STBY_W::new(self)
191    }
192    #[doc = "Bit 15"]
193    #[inline(always)]
194    #[must_use]
195    pub fn cr_pds_wb_gate_clk(&mut self) -> CR_PDS_WB_GATE_CLK_W<15> {
196        CR_PDS_WB_GATE_CLK_W::new(self)
197    }
198    #[doc = "Bit 24"]
199    #[inline(always)]
200    #[must_use]
201    pub fn cr_pds_misc_pwr_off(&mut self) -> CR_PDS_MISC_PWR_OFF_W<24> {
202        CR_PDS_MISC_PWR_OFF_W::new(self)
203    }
204    #[doc = "Bit 25"]
205    #[inline(always)]
206    #[must_use]
207    pub fn cr_pds_misc_reset(&mut self) -> CR_PDS_MISC_RESET_W<25> {
208        CR_PDS_MISC_RESET_W::new(self)
209    }
210    #[doc = "Bit 26"]
211    #[inline(always)]
212    #[must_use]
213    pub fn cr_pds_misc_mem_stby(&mut self) -> CR_PDS_MISC_MEM_STBY_W<26> {
214        CR_PDS_MISC_MEM_STBY_W::new(self)
215    }
216    #[doc = "Bit 27"]
217    #[inline(always)]
218    #[must_use]
219    pub fn cr_pds_misc_gate_clk(&mut self) -> CR_PDS_MISC_GATE_CLK_W<27> {
220        CR_PDS_MISC_GATE_CLK_W::new(self)
221    }
222    #[doc = "Writes raw bits to the register."]
223    #[inline(always)]
224    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225        self.0.bits(bits);
226        self
227    }
228}
229#[doc = "PDS_CTL4.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pds_ctl4](index.html) module"]
230pub struct PDS_CTL4_SPEC;
231impl crate::RegisterSpec for PDS_CTL4_SPEC {
232    type Ux = u32;
233}
234#[doc = "`read()` method returns [pds_ctl4::R](R) reader structure"]
235impl crate::Readable for PDS_CTL4_SPEC {
236    type Reader = R;
237}
238#[doc = "`write(|w| ..)` method takes [pds_ctl4::W](W) writer structure"]
239impl crate::Writable for PDS_CTL4_SPEC {
240    type Writer = W;
241    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
242    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
243}
244#[doc = "`reset()` method sets PDS_CTL4 to value 0x0f00_f00f"]
245impl crate::Resettable for PDS_CTL4_SPEC {
246    const RESET_VALUE: Self::Ux = 0x0f00_f00f;
247}
bl602_pac/pds/pds_ctl4.rs

bl602_pac/pds/
pds_ctl4.rs
