1#[doc = "Register `HBN_CTL` reader"]
2pub struct R(crate::R<HBN_CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HBN_CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HBN_CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HBN_CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HBN_CTL` writer"]
17pub struct W(crate::W<HBN_CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HBN_CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HBN_CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HBN_CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `rtc_ctl` reader - "]
38pub type RTC_CTL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `rtc_ctl` writer - "]
40pub type RTC_CTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 7, O>;
41#[doc = "Field `hbn_mode` writer - "]
42pub type HBN_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
43#[doc = "Field `trap_mode` reader - "]
44pub type TRAP_MODE_R = crate::BitReader<bool>;
45#[doc = "Field `pwrdn_hbn_core` reader - "]
46pub type PWRDN_HBN_CORE_R = crate::BitReader<bool>;
47#[doc = "Field `pwrdn_hbn_core` writer - "]
48pub type PWRDN_HBN_CORE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
49#[doc = "Field `pwrdn_hbn_rtc` reader - "]
50pub type PWRDN_HBN_RTC_R = crate::BitReader<bool>;
51#[doc = "Field `pwrdn_hbn_rtc` writer - "]
52pub type PWRDN_HBN_RTC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
53#[doc = "Field `sw_rst` reader - "]
54pub type SW_RST_R = crate::BitReader<bool>;
55#[doc = "Field `sw_rst` writer - "]
56pub type SW_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
57#[doc = "Field `hbn_dis_pwr_off_ldo11` reader - "]
58pub type HBN_DIS_PWR_OFF_LDO11_R = crate::BitReader<bool>;
59#[doc = "Field `hbn_dis_pwr_off_ldo11` writer - "]
60pub type HBN_DIS_PWR_OFF_LDO11_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
62#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` reader - "]
63pub type HBN_DIS_PWR_OFF_LDO11_RT_R = crate::BitReader<bool>;
64#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` writer - "]
65pub type HBN_DIS_PWR_OFF_LDO11_RT_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
67#[doc = "Field `hbn_ldo11_rt_vout_sel` reader - "]
68pub type HBN_LDO11_RT_VOUT_SEL_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `hbn_ldo11_rt_vout_sel` writer - "]
70pub type HBN_LDO11_RT_VOUT_SEL_W<'a, const O: u8> =
71 crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 4, O>;
72#[doc = "Field `hbn_ldo11_aon_vout_sel` reader - "]
73pub type HBN_LDO11_AON_VOUT_SEL_R = crate::FieldReader<u8, u8>;
74#[doc = "Field `hbn_ldo11_aon_vout_sel` writer - "]
75pub type HBN_LDO11_AON_VOUT_SEL_W<'a, const O: u8> =
76 crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 4, O>;
77#[doc = "Field `pu_dcdc18_aon` reader - "]
78pub type PU_DCDC18_AON_R = crate::BitReader<bool>;
79#[doc = "Field `pu_dcdc18_aon` writer - "]
80pub type PU_DCDC18_AON_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
81#[doc = "Field `rtc_dly_option` reader - "]
82pub type RTC_DLY_OPTION_R = crate::BitReader<bool>;
83#[doc = "Field `rtc_dly_option` writer - "]
84pub type RTC_DLY_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
85#[doc = "Field `pwr_on_option` reader - "]
86pub type PWR_ON_OPTION_R = crate::BitReader<bool>;
87#[doc = "Field `pwr_on_option` writer - "]
88pub type PWR_ON_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
89#[doc = "Field `sram_slp_option` reader - "]
90pub type SRAM_SLP_OPTION_R = crate::BitReader<bool>;
91#[doc = "Field `sram_slp_option` writer - "]
92pub type SRAM_SLP_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
93#[doc = "Field `sram_slp` reader - "]
94pub type SRAM_SLP_R = crate::BitReader<bool>;
95#[doc = "Field `hbn_state` reader - "]
96pub type HBN_STATE_R = crate::FieldReader<u8, u8>;
97impl R {
98 #[doc = "Bits 0:6"]
99 #[inline(always)]
100 pub fn rtc_ctl(&self) -> RTC_CTL_R {
101 RTC_CTL_R::new((self.bits & 0x7f) as u8)
102 }
103 #[doc = "Bit 8"]
104 #[inline(always)]
105 pub fn trap_mode(&self) -> TRAP_MODE_R {
106 TRAP_MODE_R::new(((self.bits >> 8) & 1) != 0)
107 }
108 #[doc = "Bit 9"]
109 #[inline(always)]
110 pub fn pwrdn_hbn_core(&self) -> PWRDN_HBN_CORE_R {
111 PWRDN_HBN_CORE_R::new(((self.bits >> 9) & 1) != 0)
112 }
113 #[doc = "Bit 11"]
114 #[inline(always)]
115 pub fn pwrdn_hbn_rtc(&self) -> PWRDN_HBN_RTC_R {
116 PWRDN_HBN_RTC_R::new(((self.bits >> 11) & 1) != 0)
117 }
118 #[doc = "Bit 12"]
119 #[inline(always)]
120 pub fn sw_rst(&self) -> SW_RST_R {
121 SW_RST_R::new(((self.bits >> 12) & 1) != 0)
122 }
123 #[doc = "Bit 13"]
124 #[inline(always)]
125 pub fn hbn_dis_pwr_off_ldo11(&self) -> HBN_DIS_PWR_OFF_LDO11_R {
126 HBN_DIS_PWR_OFF_LDO11_R::new(((self.bits >> 13) & 1) != 0)
127 }
128 #[doc = "Bit 14"]
129 #[inline(always)]
130 pub fn hbn_dis_pwr_off_ldo11_rt(&self) -> HBN_DIS_PWR_OFF_LDO11_RT_R {
131 HBN_DIS_PWR_OFF_LDO11_RT_R::new(((self.bits >> 14) & 1) != 0)
132 }
133 #[doc = "Bits 15:18"]
134 #[inline(always)]
135 pub fn hbn_ldo11_rt_vout_sel(&self) -> HBN_LDO11_RT_VOUT_SEL_R {
136 HBN_LDO11_RT_VOUT_SEL_R::new(((self.bits >> 15) & 0x0f) as u8)
137 }
138 #[doc = "Bits 19:22"]
139 #[inline(always)]
140 pub fn hbn_ldo11_aon_vout_sel(&self) -> HBN_LDO11_AON_VOUT_SEL_R {
141 HBN_LDO11_AON_VOUT_SEL_R::new(((self.bits >> 19) & 0x0f) as u8)
142 }
143 #[doc = "Bit 23"]
144 #[inline(always)]
145 pub fn pu_dcdc18_aon(&self) -> PU_DCDC18_AON_R {
146 PU_DCDC18_AON_R::new(((self.bits >> 23) & 1) != 0)
147 }
148 #[doc = "Bit 24"]
149 #[inline(always)]
150 pub fn rtc_dly_option(&self) -> RTC_DLY_OPTION_R {
151 RTC_DLY_OPTION_R::new(((self.bits >> 24) & 1) != 0)
152 }
153 #[doc = "Bit 25"]
154 #[inline(always)]
155 pub fn pwr_on_option(&self) -> PWR_ON_OPTION_R {
156 PWR_ON_OPTION_R::new(((self.bits >> 25) & 1) != 0)
157 }
158 #[doc = "Bit 26"]
159 #[inline(always)]
160 pub fn sram_slp_option(&self) -> SRAM_SLP_OPTION_R {
161 SRAM_SLP_OPTION_R::new(((self.bits >> 26) & 1) != 0)
162 }
163 #[doc = "Bit 27"]
164 #[inline(always)]
165 pub fn sram_slp(&self) -> SRAM_SLP_R {
166 SRAM_SLP_R::new(((self.bits >> 27) & 1) != 0)
167 }
168 #[doc = "Bits 28:31"]
169 #[inline(always)]
170 pub fn hbn_state(&self) -> HBN_STATE_R {
171 HBN_STATE_R::new(((self.bits >> 28) & 0x0f) as u8)
172 }
173}
174impl W {
175 #[doc = "Bits 0:6"]
176 #[inline(always)]
177 #[must_use]
178 pub fn rtc_ctl(&mut self) -> RTC_CTL_W<0> {
179 RTC_CTL_W::new(self)
180 }
181 #[doc = "Bit 7"]
182 #[inline(always)]
183 #[must_use]
184 pub fn hbn_mode(&mut self) -> HBN_MODE_W<7> {
185 HBN_MODE_W::new(self)
186 }
187 #[doc = "Bit 9"]
188 #[inline(always)]
189 #[must_use]
190 pub fn pwrdn_hbn_core(&mut self) -> PWRDN_HBN_CORE_W<9> {
191 PWRDN_HBN_CORE_W::new(self)
192 }
193 #[doc = "Bit 11"]
194 #[inline(always)]
195 #[must_use]
196 pub fn pwrdn_hbn_rtc(&mut self) -> PWRDN_HBN_RTC_W<11> {
197 PWRDN_HBN_RTC_W::new(self)
198 }
199 #[doc = "Bit 12"]
200 #[inline(always)]
201 #[must_use]
202 pub fn sw_rst(&mut self) -> SW_RST_W<12> {
203 SW_RST_W::new(self)
204 }
205 #[doc = "Bit 13"]
206 #[inline(always)]
207 #[must_use]
208 pub fn hbn_dis_pwr_off_ldo11(&mut self) -> HBN_DIS_PWR_OFF_LDO11_W<13> {
209 HBN_DIS_PWR_OFF_LDO11_W::new(self)
210 }
211 #[doc = "Bit 14"]
212 #[inline(always)]
213 #[must_use]
214 pub fn hbn_dis_pwr_off_ldo11_rt(&mut self) -> HBN_DIS_PWR_OFF_LDO11_RT_W<14> {
215 HBN_DIS_PWR_OFF_LDO11_RT_W::new(self)
216 }
217 #[doc = "Bits 15:18"]
218 #[inline(always)]
219 #[must_use]
220 pub fn hbn_ldo11_rt_vout_sel(&mut self) -> HBN_LDO11_RT_VOUT_SEL_W<15> {
221 HBN_LDO11_RT_VOUT_SEL_W::new(self)
222 }
223 #[doc = "Bits 19:22"]
224 #[inline(always)]
225 #[must_use]
226 pub fn hbn_ldo11_aon_vout_sel(&mut self) -> HBN_LDO11_AON_VOUT_SEL_W<19> {
227 HBN_LDO11_AON_VOUT_SEL_W::new(self)
228 }
229 #[doc = "Bit 23"]
230 #[inline(always)]
231 #[must_use]
232 pub fn pu_dcdc18_aon(&mut self) -> PU_DCDC18_AON_W<23> {
233 PU_DCDC18_AON_W::new(self)
234 }
235 #[doc = "Bit 24"]
236 #[inline(always)]
237 #[must_use]
238 pub fn rtc_dly_option(&mut self) -> RTC_DLY_OPTION_W<24> {
239 RTC_DLY_OPTION_W::new(self)
240 }
241 #[doc = "Bit 25"]
242 #[inline(always)]
243 #[must_use]
244 pub fn pwr_on_option(&mut self) -> PWR_ON_OPTION_W<25> {
245 PWR_ON_OPTION_W::new(self)
246 }
247 #[doc = "Bit 26"]
248 #[inline(always)]
249 #[must_use]
250 pub fn sram_slp_option(&mut self) -> SRAM_SLP_OPTION_W<26> {
251 SRAM_SLP_OPTION_W::new(self)
252 }
253 #[doc = "Writes raw bits to the register."]
254 #[inline(always)]
255 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
256 self.0.bits(bits);
257 self
258 }
259}
260#[doc = "HBN_CTL.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hbn_ctl](index.html) module"]
261pub struct HBN_CTL_SPEC;
262impl crate::RegisterSpec for HBN_CTL_SPEC {
263 type Ux = u32;
264}
265#[doc = "`read()` method returns [hbn_ctl::R](R) reader structure"]
266impl crate::Readable for HBN_CTL_SPEC {
267 type Reader = R;
268}
269#[doc = "`write(|w| ..)` method takes [hbn_ctl::W](W) writer structure"]
270impl crate::Writable for HBN_CTL_SPEC {
271 type Writer = W;
272 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
273 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
274}
275#[doc = "`reset()` method sets HBN_CTL to value 0x00d5_0000"]
276impl crate::Resettable for HBN_CTL_SPEC {
277 const RESET_VALUE: Self::Ux = 0x00d5_0000;
278}