bl602_pac/glb/
clk_cfg1.rs

1#[doc = "Register `clk_cfg1` reader"]
2pub struct R(crate::R<CLK_CFG1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CFG1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CFG1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CFG1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `clk_cfg1` writer"]
17pub struct W(crate::W<CLK_CFG1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_CFG1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_CFG1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_CFG1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `wifi_mac_core_div` reader - WiFi core clock divider (0: 80MHz, 1: 40MHz)"]
38pub type WIFI_MAC_CORE_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `wifi_mac_core_div` writer - WiFi core clock divider (0: 80MHz, 1: 40MHz)"]
40pub type WIFI_MAC_CORE_DIV_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 4, O>;
42#[doc = "Field `wifi_mac_wt_div` reader - WiFi encryption clock divider"]
43pub type WIFI_MAC_WT_DIV_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `wifi_mac_wt_div` writer - WiFi encryption clock divider"]
45pub type WIFI_MAC_WT_DIV_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 4, O>;
47#[doc = "Field `ble_clk_sel` reader - "]
48pub type BLE_CLK_SEL_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `ble_clk_sel` writer - "]
50pub type BLE_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 6, O>;
51#[doc = "Field `ble_en` reader - Bluetooth clock enable"]
52pub type BLE_EN_R = crate::BitReader<bool>;
53#[doc = "Field `ble_en` writer - Bluetooth clock enable"]
54pub type BLE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
55impl R {
56    #[doc = "Bits 0:3 - WiFi core clock divider (0: 80MHz, 1: 40MHz)"]
57    #[inline(always)]
58    pub fn wifi_mac_core_div(&self) -> WIFI_MAC_CORE_DIV_R {
59        WIFI_MAC_CORE_DIV_R::new((self.bits & 0x0f) as u8)
60    }
61    #[doc = "Bits 4:7 - WiFi encryption clock divider"]
62    #[inline(always)]
63    pub fn wifi_mac_wt_div(&self) -> WIFI_MAC_WT_DIV_R {
64        WIFI_MAC_WT_DIV_R::new(((self.bits >> 4) & 0x0f) as u8)
65    }
66    #[doc = "Bits 16:21"]
67    #[inline(always)]
68    pub fn ble_clk_sel(&self) -> BLE_CLK_SEL_R {
69        BLE_CLK_SEL_R::new(((self.bits >> 16) & 0x3f) as u8)
70    }
71    #[doc = "Bit 24 - Bluetooth clock enable"]
72    #[inline(always)]
73    pub fn ble_en(&self) -> BLE_EN_R {
74        BLE_EN_R::new(((self.bits >> 24) & 1) != 0)
75    }
76}
77impl W {
78    #[doc = "Bits 0:3 - WiFi core clock divider (0: 80MHz, 1: 40MHz)"]
79    #[inline(always)]
80    #[must_use]
81    pub fn wifi_mac_core_div(&mut self) -> WIFI_MAC_CORE_DIV_W<0> {
82        WIFI_MAC_CORE_DIV_W::new(self)
83    }
84    #[doc = "Bits 4:7 - WiFi encryption clock divider"]
85    #[inline(always)]
86    #[must_use]
87    pub fn wifi_mac_wt_div(&mut self) -> WIFI_MAC_WT_DIV_W<4> {
88        WIFI_MAC_WT_DIV_W::new(self)
89    }
90    #[doc = "Bits 16:21"]
91    #[inline(always)]
92    #[must_use]
93    pub fn ble_clk_sel(&mut self) -> BLE_CLK_SEL_W<16> {
94        BLE_CLK_SEL_W::new(self)
95    }
96    #[doc = "Bit 24 - Bluetooth clock enable"]
97    #[inline(always)]
98    #[must_use]
99    pub fn ble_en(&mut self) -> BLE_EN_W<24> {
100        BLE_EN_W::new(self)
101    }
102    #[doc = "Writes raw bits to the register."]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.0.bits(bits);
106        self
107    }
108}
109#[doc = "clk_cfg1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg1](index.html) module"]
110pub struct CLK_CFG1_SPEC;
111impl crate::RegisterSpec for CLK_CFG1_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [clk_cfg1::R](R) reader structure"]
115impl crate::Readable for CLK_CFG1_SPEC {
116    type Reader = R;
117}
118#[doc = "`write(|w| ..)` method takes [clk_cfg1::W](W) writer structure"]
119impl crate::Writable for CLK_CFG1_SPEC {
120    type Writer = W;
121    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123}
124#[doc = "`reset()` method sets clk_cfg1 to value 0x0110_0001"]
125impl crate::Resettable for CLK_CFG1_SPEC {
126    const RESET_VALUE: Self::Ux = 0x0110_0001;
127}
bl602_pac/glb/clk_cfg1.rs

bl602_pac/glb/
clk_cfg1.rs
