bl602_pac/glb/
clk_cfg0.rs

1#[doc = "Register `clk_cfg0` reader"]
2pub struct R(crate::R<CLK_CFG0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CFG0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CFG0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CFG0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `clk_cfg0` writer"]
17pub struct W(crate::W<CLK_CFG0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_CFG0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_CFG0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_CFG0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `reg_pll_en` reader - PLL enable"]
38pub type REG_PLL_EN_R = crate::BitReader<bool>;
39#[doc = "Field `reg_pll_en` writer - PLL enable"]
40pub type REG_PLL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
41#[doc = "Field `reg_fclk_en` reader - "]
42pub type REG_FCLK_EN_R = crate::BitReader<bool>;
43#[doc = "Field `reg_fclk_en` writer - "]
44pub type REG_FCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
45#[doc = "Field `reg_hclk_en` reader - MCU clock enable"]
46pub type REG_HCLK_EN_R = crate::BitReader<bool>;
47#[doc = "Field `reg_hclk_en` writer - MCU clock enable"]
48pub type REG_HCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
49#[doc = "Field `reg_bclk_en` reader - Base clock enable"]
50pub type REG_BCLK_EN_R = crate::BitReader<bool>;
51#[doc = "Field `reg_bclk_en` writer - Base clock enable"]
52pub type REG_BCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
53#[doc = "Field `reg_pll_sel` reader - PLL clock selection (0: 48MHz, 1: 120MHz, 2: 160MHz and 3: 192MHz)"]
54pub type REG_PLL_SEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `reg_pll_sel` writer - PLL clock selection (0: 48MHz, 1: 120MHz, 2: 160MHz and 3: 192MHz)"]
56pub type REG_PLL_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 2, O>;
57#[doc = "Field `hbn_root_clk_sel` reader - "]
58pub type HBN_ROOT_CLK_SEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `reg_hclk_div` reader - MCU clock divider"]
60pub type REG_HCLK_DIV_R = crate::FieldReader<u8, u8>;
61#[doc = "Field `reg_hclk_div` writer - MCU clock divider"]
62pub type REG_HCLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 8, O>;
63#[doc = "Field `reg_bclk_div` reader - Base clock divider"]
64pub type REG_BCLK_DIV_R = crate::FieldReader<u8, u8>;
65#[doc = "Field `reg_bclk_div` writer - Base clock divider"]
66pub type REG_BCLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 8, O>;
67#[doc = "Field `fclk_sw_state` reader - "]
68pub type FCLK_SW_STATE_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `chip_rdy` reader - "]
70pub type CHIP_RDY_R = crate::BitReader<bool>;
71#[doc = "Field `glb_id` reader - "]
72pub type GLB_ID_R = crate::FieldReader<u8, u8>;
73impl R {
74    #[doc = "Bit 0 - PLL enable"]
75    #[inline(always)]
76    pub fn reg_pll_en(&self) -> REG_PLL_EN_R {
77        REG_PLL_EN_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1"]
80    #[inline(always)]
81    pub fn reg_fclk_en(&self) -> REG_FCLK_EN_R {
82        REG_FCLK_EN_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - MCU clock enable"]
85    #[inline(always)]
86    pub fn reg_hclk_en(&self) -> REG_HCLK_EN_R {
87        REG_HCLK_EN_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - Base clock enable"]
90    #[inline(always)]
91    pub fn reg_bclk_en(&self) -> REG_BCLK_EN_R {
92        REG_BCLK_EN_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bits 4:5 - PLL clock selection (0: 48MHz, 1: 120MHz, 2: 160MHz and 3: 192MHz)"]
95    #[inline(always)]
96    pub fn reg_pll_sel(&self) -> REG_PLL_SEL_R {
97        REG_PLL_SEL_R::new(((self.bits >> 4) & 3) as u8)
98    }
99    #[doc = "Bits 6:7"]
100    #[inline(always)]
101    pub fn hbn_root_clk_sel(&self) -> HBN_ROOT_CLK_SEL_R {
102        HBN_ROOT_CLK_SEL_R::new(((self.bits >> 6) & 3) as u8)
103    }
104    #[doc = "Bits 8:15 - MCU clock divider"]
105    #[inline(always)]
106    pub fn reg_hclk_div(&self) -> REG_HCLK_DIV_R {
107        REG_HCLK_DIV_R::new(((self.bits >> 8) & 0xff) as u8)
108    }
109    #[doc = "Bits 16:23 - Base clock divider"]
110    #[inline(always)]
111    pub fn reg_bclk_div(&self) -> REG_BCLK_DIV_R {
112        REG_BCLK_DIV_R::new(((self.bits >> 16) & 0xff) as u8)
113    }
114    #[doc = "Bits 24:26"]
115    #[inline(always)]
116    pub fn fclk_sw_state(&self) -> FCLK_SW_STATE_R {
117        FCLK_SW_STATE_R::new(((self.bits >> 24) & 7) as u8)
118    }
119    #[doc = "Bit 27"]
120    #[inline(always)]
121    pub fn chip_rdy(&self) -> CHIP_RDY_R {
122        CHIP_RDY_R::new(((self.bits >> 27) & 1) != 0)
123    }
124    #[doc = "Bits 28:31"]
125    #[inline(always)]
126    pub fn glb_id(&self) -> GLB_ID_R {
127        GLB_ID_R::new(((self.bits >> 28) & 0x0f) as u8)
128    }
129}
130impl W {
131    #[doc = "Bit 0 - PLL enable"]
132    #[inline(always)]
133    #[must_use]
134    pub fn reg_pll_en(&mut self) -> REG_PLL_EN_W<0> {
135        REG_PLL_EN_W::new(self)
136    }
137    #[doc = "Bit 1"]
138    #[inline(always)]
139    #[must_use]
140    pub fn reg_fclk_en(&mut self) -> REG_FCLK_EN_W<1> {
141        REG_FCLK_EN_W::new(self)
142    }
143    #[doc = "Bit 2 - MCU clock enable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn reg_hclk_en(&mut self) -> REG_HCLK_EN_W<2> {
147        REG_HCLK_EN_W::new(self)
148    }
149    #[doc = "Bit 3 - Base clock enable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn reg_bclk_en(&mut self) -> REG_BCLK_EN_W<3> {
153        REG_BCLK_EN_W::new(self)
154    }
155    #[doc = "Bits 4:5 - PLL clock selection (0: 48MHz, 1: 120MHz, 2: 160MHz and 3: 192MHz)"]
156    #[inline(always)]
157    #[must_use]
158    pub fn reg_pll_sel(&mut self) -> REG_PLL_SEL_W<4> {
159        REG_PLL_SEL_W::new(self)
160    }
161    #[doc = "Bits 8:15 - MCU clock divider"]
162    #[inline(always)]
163    #[must_use]
164    pub fn reg_hclk_div(&mut self) -> REG_HCLK_DIV_W<8> {
165        REG_HCLK_DIV_W::new(self)
166    }
167    #[doc = "Bits 16:23 - Base clock divider"]
168    #[inline(always)]
169    #[must_use]
170    pub fn reg_bclk_div(&mut self) -> REG_BCLK_DIV_W<16> {
171        REG_BCLK_DIV_W::new(self)
172    }
173    #[doc = "Writes raw bits to the register."]
174    #[inline(always)]
175    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
176        self.0.bits(bits);
177        self
178    }
179}
180#[doc = "Clock configuration for processor and bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg0](index.html) module"]
181pub struct CLK_CFG0_SPEC;
182impl crate::RegisterSpec for CLK_CFG0_SPEC {
183    type Ux = u32;
184}
185#[doc = "`read()` method returns [clk_cfg0::R](R) reader structure"]
186impl crate::Readable for CLK_CFG0_SPEC {
187    type Reader = R;
188}
189#[doc = "`write(|w| ..)` method takes [clk_cfg0::W](W) writer structure"]
190impl crate::Writable for CLK_CFG0_SPEC {
191    type Writer = W;
192    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
193    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194}
195#[doc = "`reset()` method sets clk_cfg0 to value 0x6000_000f"]
196impl crate::Resettable for CLK_CFG0_SPEC {
197    const RESET_VALUE: Self::Ux = 0x6000_000f;
198}
bl602_pac/glb/clk_cfg0.rs

bl602_pac/glb/
clk_cfg0.rs
