1#[doc = "Register `adda2` reader"]
2pub struct R(crate::R<ADDA2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADDA2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADDA2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADDA2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `adda2` writer"]
17pub struct W(crate::W<ADDA2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADDA2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADDA2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADDA2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `adc_vref_sel` reader - "]
38pub type ADC_VREF_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `adc_vref_sel` writer - "]
40pub type ADC_VREF_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
41#[doc = "Field `adc_dly_ctl` reader - "]
42pub type ADC_DLY_CTL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `adc_dly_ctl` writer - "]
44pub type ADC_DLY_CTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
45#[doc = "Field `adc_dvdd_sel` reader - "]
46pub type ADC_DVDD_SEL_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `adc_dvdd_sel` writer - "]
48pub type ADC_DVDD_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
49#[doc = "Field `adc_sar_ascal_en` reader - "]
50pub type ADC_SAR_ASCAL_EN_R = crate::BitReader<bool>;
51#[doc = "Field `adc_sar_ascal_en` writer - "]
52pub type ADC_SAR_ASCAL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
53#[doc = "Field `adc_gt_rm` reader - "]
54pub type ADC_GT_RM_R = crate::BitReader<bool>;
55#[doc = "Field `adc_gt_rm` writer - "]
56pub type ADC_GT_RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
57#[doc = "Field `adc_clk_sync_inv` reader - "]
58pub type ADC_CLK_SYNC_INV_R = crate::BitReader<bool>;
59#[doc = "Field `adc_clk_sync_inv` writer - "]
60pub type ADC_CLK_SYNC_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
61#[doc = "Field `adc_clk_inv` reader - "]
62pub type ADC_CLK_INV_R = crate::BitReader<bool>;
63#[doc = "Field `adc_clk_inv` writer - "]
64pub type ADC_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
65#[doc = "Field `adc_clk_div_sel` reader - "]
66pub type ADC_CLK_DIV_SEL_R = crate::BitReader<bool>;
67#[doc = "Field `adc_clk_div_sel` writer - "]
68pub type ADC_CLK_DIV_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
69impl R {
70 #[doc = "Bits 0:1"]
71 #[inline(always)]
72 pub fn adc_vref_sel(&self) -> ADC_VREF_SEL_R {
73 ADC_VREF_SEL_R::new((self.bits & 3) as u8)
74 }
75 #[doc = "Bits 4:5"]
76 #[inline(always)]
77 pub fn adc_dly_ctl(&self) -> ADC_DLY_CTL_R {
78 ADC_DLY_CTL_R::new(((self.bits >> 4) & 3) as u8)
79 }
80 #[doc = "Bits 8:9"]
81 #[inline(always)]
82 pub fn adc_dvdd_sel(&self) -> ADC_DVDD_SEL_R {
83 ADC_DVDD_SEL_R::new(((self.bits >> 8) & 3) as u8)
84 }
85 #[doc = "Bit 12"]
86 #[inline(always)]
87 pub fn adc_sar_ascal_en(&self) -> ADC_SAR_ASCAL_EN_R {
88 ADC_SAR_ASCAL_EN_R::new(((self.bits >> 12) & 1) != 0)
89 }
90 #[doc = "Bit 16"]
91 #[inline(always)]
92 pub fn adc_gt_rm(&self) -> ADC_GT_RM_R {
93 ADC_GT_RM_R::new(((self.bits >> 16) & 1) != 0)
94 }
95 #[doc = "Bit 20"]
96 #[inline(always)]
97 pub fn adc_clk_sync_inv(&self) -> ADC_CLK_SYNC_INV_R {
98 ADC_CLK_SYNC_INV_R::new(((self.bits >> 20) & 1) != 0)
99 }
100 #[doc = "Bit 24"]
101 #[inline(always)]
102 pub fn adc_clk_inv(&self) -> ADC_CLK_INV_R {
103 ADC_CLK_INV_R::new(((self.bits >> 24) & 1) != 0)
104 }
105 #[doc = "Bit 28"]
106 #[inline(always)]
107 pub fn adc_clk_div_sel(&self) -> ADC_CLK_DIV_SEL_R {
108 ADC_CLK_DIV_SEL_R::new(((self.bits >> 28) & 1) != 0)
109 }
110}
111impl W {
112 #[doc = "Bits 0:1"]
113 #[inline(always)]
114 #[must_use]
115 pub fn adc_vref_sel(&mut self) -> ADC_VREF_SEL_W<0> {
116 ADC_VREF_SEL_W::new(self)
117 }
118 #[doc = "Bits 4:5"]
119 #[inline(always)]
120 #[must_use]
121 pub fn adc_dly_ctl(&mut self) -> ADC_DLY_CTL_W<4> {
122 ADC_DLY_CTL_W::new(self)
123 }
124 #[doc = "Bits 8:9"]
125 #[inline(always)]
126 #[must_use]
127 pub fn adc_dvdd_sel(&mut self) -> ADC_DVDD_SEL_W<8> {
128 ADC_DVDD_SEL_W::new(self)
129 }
130 #[doc = "Bit 12"]
131 #[inline(always)]
132 #[must_use]
133 pub fn adc_sar_ascal_en(&mut self) -> ADC_SAR_ASCAL_EN_W<12> {
134 ADC_SAR_ASCAL_EN_W::new(self)
135 }
136 #[doc = "Bit 16"]
137 #[inline(always)]
138 #[must_use]
139 pub fn adc_gt_rm(&mut self) -> ADC_GT_RM_W<16> {
140 ADC_GT_RM_W::new(self)
141 }
142 #[doc = "Bit 20"]
143 #[inline(always)]
144 #[must_use]
145 pub fn adc_clk_sync_inv(&mut self) -> ADC_CLK_SYNC_INV_W<20> {
146 ADC_CLK_SYNC_INV_W::new(self)
147 }
148 #[doc = "Bit 24"]
149 #[inline(always)]
150 #[must_use]
151 pub fn adc_clk_inv(&mut self) -> ADC_CLK_INV_W<24> {
152 ADC_CLK_INV_W::new(self)
153 }
154 #[doc = "Bit 28"]
155 #[inline(always)]
156 #[must_use]
157 pub fn adc_clk_div_sel(&mut self) -> ADC_CLK_DIV_SEL_W<28> {
158 ADC_CLK_DIV_SEL_W::new(self)
159 }
160 #[doc = "Writes raw bits to the register."]
161 #[inline(always)]
162 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163 self.0.bits(bits);
164 self
165 }
166}
167#[doc = "adda2.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adda2](index.html) module"]
168pub struct ADDA2_SPEC;
169impl crate::RegisterSpec for ADDA2_SPEC {
170 type Ux = u32;
171}
172#[doc = "`read()` method returns [adda2::R](R) reader structure"]
173impl crate::Readable for ADDA2_SPEC {
174 type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [adda2::W](W) writer structure"]
177impl crate::Writable for ADDA2_SPEC {
178 type Writer = W;
179 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets adda2 to value 0"]
183impl crate::Resettable for ADDA2_SPEC {
184 const RESET_VALUE: Self::Ux = 0;
185}