Crate bhc_loop_ir 

BHC Loop IR

This crate defines the Loop Intermediate Representation for the Basel Haskell Compiler. Loop IR makes iteration structure explicit and is the target for vectorization and low-level optimization.

Overview

Loop IR is the lowest-level IR before code generation. It provides:

• Explicit iteration: Loops with bounds and strides
• Vectorization information: Which loops can be SIMD-ized
• Parallelization hints: Which loops can run in parallel
• Memory access patterns: For cache optimization

IR Pipeline Position

Source Code
    |
    v
[Parse/AST]
    |
    v
[HIR]
    |
    v
[Core IR]
    |
    v
[Tensor IR]  <- High-level tensor operations
    |
    v
[Loop IR]    <- This crate: explicit iteration
    |
    v
[Codegen]    <- LLVM IR / Native code

Key Transformations

Loop IR supports several important optimizations:

1. Loop tiling: Break loops into cache-friendly tiles
2. Vectorization: Convert scalar operations to SIMD
3. Parallelization: Mark loops for parallel execution
4. Interchange: Reorder loops for better memory access
5. Unrolling: Reduce loop overhead

Main Types

• LoopIR: The top-level IR structure
• Loop: A single loop with bounds and body
• Stmt: Statements within loop bodies
• Value: SSA values (registers)
• MemRef: Memory references with access patterns

M3 Deliverables

This crate implements the following M3 features:

• SIMD Types: LoopType::VEC4F32, LoopType::VEC8F32, LoopType::VEC2F64, LoopType::VEC4F64
• Auto-vectorization: vectorize::VectorizePass
• Parallel primitives: parallel::ParFor, parallel::ParMap, parallel::ParReduce
• SIMD intrinsics: vectorize::SimdIntrinsic

See Also

• bhc-tensor-ir: Tensor IR that lowers to Loop IR
• bhc-codegen: Code generation from Loop IR
• H26-SPEC Section 7: Tensor Model (lowering)

Re-exports

pub use lower::lower_kernel;

pub use lower::lower_kernels;

pub use lower::LowerConfig;

pub use lower::LowerError;

pub use parallel::ParFor;

pub use parallel::ParMap;

pub use parallel::ParReduce;

pub use parallel::ParallelConfig;

pub use parallel::ParallelPass;

pub use parallel::ParallelStrategy;

pub use parallel::Range;

pub use vectorize::SimdIntrinsic;

pub use vectorize::VectorizeConfig;

pub use vectorize::VectorizePass;

pub use vectorize::VectorizeReport;

Modules

lower

Lowering from Tensor IR to Loop IR

parallel

Parallel Loop Primitives

vectorize

Auto-Vectorization Pass

Structs

AffineAccess

Affine memory access pattern.

Alloc

A memory allocation.

BlockId

A unique identifier for basic blocks.

Body

The body of a function or loop.

IfStmt

A conditional statement.

Loop

A loop construct.

LoopAttrs

Loop attributes for optimization.

LoopDependency

A dependency between loops.

LoopIR

The main Loop IR structure.

LoopId

A unique identifier for loops.

LoopMetadata

Loop metadata for optimization.

MemRef

A memory reference.

Param

A function parameter.

ValueId

A unique identifier for values (SSA registers).

Enums

AccessPattern

Memory access patterns for optimization.

AllocSize

Size of an allocation.

BarrierKind

Barrier kinds for synchronization.

BinOp

Binary operations.

CmpOp

Comparison operations.

DependencyKind

Kinds of dependencies.

LoopIrError

Errors in Loop IR.

LoopType

Types in Loop IR.

Op

Operations in Loop IR.

ReduceOp

Reduction operations.

ScalarType

Scalar types in Loop IR.

Stmt

Statements in Loop IR.

TargetArch

Target architecture for vectorization decisions.

TripCount

Trip count information.

UnOp

Unary operations.

Value

A value (SSA reference or constant).