bgt60trxx/
register.rs

1
2use bitfield_struct::bitfield;
3
4// See also https://github.com/Infineon/sensor-xensiv-bgt60trxx/blob/master/xensiv_bgt60trxx_regs.h
5
6#[allow(non_camel_case_types)]
7#[allow(dead_code)]
8#[repr(u8)]
9#[derive(Debug, Clone, Copy)]
10pub enum Register {
11    MAIN = 0x00,
12    ADC0 = 0x01,
13    CHIP_ID = 0x02,
14    STAT1 = 0x03,
15    PACR1 = 0x04,
16    PACR2 = 0x05,
17    SFCTL = 0x06,
18    SADC_CTRL = 0x07,
19    CSI_0 = 0x08,
20    CSI_1 = 0x09,
21    CSI_2 = 0x0A,
22    CSCI = 0x0B,
23    CSDS_0 = 0x0C,
24    CSDS_1 = 0x0D,
25    CSDS_2 = 0x0E,
26    CSCDS = 0x0F,
27    CSU1_0 = 0x10,
28    CSU1_1 = 0x11,
29    CSU1_2 = 0x12,
30    CSD1_0 = 0x13,
31    CSD1_1 = 0x14,
32    CSD1_2 = 0x15,
33    CSC1 = 0x16,
34    CSU2_0 = 0x17,
35    CSU2_1 = 0x18,
36    CSU2_2 = 0x19,
37    CSD2_0 = 0x1A,
38    CSD2_1 = 0x1B,
39    CSD2_2 = 0x1C,
40    CSC2 = 0x1D,
41    CSU3_0 = 0x1E,
42    CSU3_1 = 0x1F,
43    CSU3_2 = 0x20,
44    CSD3_0 = 0x21,
45    CSD3_1 = 0x22,
46    CSD3_2 = 0x23,
47    CSC3 = 0x24,
48    CSU4_0 = 0x25,
49    CSU4_1 = 0x26,
50    CSU4_2 = 0x27,
51    CSD4_0 = 0x28,
52    CSD4_1 = 0x29,
53    CSD4_2 = 0x2A,
54    CSC4 = 0x2B,
55    CCR0 = 0x2C,
56    CCR1 = 0x2D,
57    CCR2 = 0x2E,
58    CCR3 = 0x2F,
59    PLL1_0 = 0x30,
60    PLL1_1 = 0x31,
61    PLL1_2 = 0x32,
62    PLL1_3 = 0x33,
63    PLL1_4 = 0x34,
64    PLL1_5 = 0x35,
65    PLL1_6 = 0x36,
66    PLL1_7 = 0x37,
67    PLL2_0 = 0x38,
68    PLL2_1 = 0x39,
69    PLL2_2 = 0x3A,
70    PLL2_3 = 0x3B,
71    PLL2_4 = 0x3C,
72    PLL2_5 = 0x3D,
73    PLL2_6 = 0x3E,
74    PLL2_7 = 0x3F,
75    PLL3_0 = 0x40,
76    PLL3_1 = 0x41,
77    PLL3_2 = 0x42,
78    PLL3_3 = 0x43,
79    PLL3_4 = 0x44,
80    PLL3_5 = 0x45,
81    PLL3_6 = 0x46,
82    PLL3_7 = 0x47,
83    PLL4_0 = 0x48,
84    PLL4_1 = 0x49,
85    PLL4_2 = 0x4A,
86    PLL4_3 = 0x4B,
87    PLL4_4 = 0x4C,
88    PLL4_5 = 0x4D,
89    PLL4_6 = 0x4E,
90    PLL4_7 = 0x4F,
91    RFT0 = 0x55,
92    RFT1 = 0x56,
93    PLL_DFT0 = 0x59,
94    STAT0 = 0x5D,
95    SADC_RESULT = 0x5E,
96    FSTAT_TR13C = 0x5F,
97    FIFO_TR13C = 0x60,
98    FSTAT_UTR11 = 0x63,
99    FIFO_UTR11 = 0x64
100}
101
102#[bitfield(u32)]
103#[allow(non_camel_case_types)]
104pub struct MAIN {
105    #[bits(1, access = WO)]
106    pub frame_start: bool,
107    #[bits(1)]
108    pub sw_reset: bool,
109    #[bits(1)]
110    pub fsm_reset: bool,
111    #[bits(1)]
112    pub fifo_reset: bool,
113    #[bits(8)]
114    pub tr_wkup: usize,
115    #[bits(4)]
116    pub tw_wkup_mul: usize,
117    #[bits(1)]
118    pub cw_mode: bool,
119    #[bits(2)] 
120    pub sadc_clkdiv: usize,
121    #[bits(2)]
122    pub bg_clk_div: usize,
123    #[bits(2)]
124    pub load_strength: usize,
125    pub ldo_mode: bool,
126    #[bits(8)] // padding
127    __: usize,
128}
129
130#[bitfield(u32)]
131#[allow(non_camel_case_types)]
132pub struct CHIP_ID {
133    #[bits(8, access = RO)]
134    pub rf_id: usize,
135    #[bits(16, access = RO)]
136    pub digital_id: usize,
137    #[bits(8)]
138    __: usize,
139}
140
141#[bitfield(u32)]
142#[allow(non_camel_case_types)]
143pub struct STAT1 {
144    #[bits(12, access = RO)]
145    pub shape_grp_cnt: usize,
146    #[bits(12, access = RO)]
147    pub frame_cnt: usize,
148    #[bits(8)]
149    __: usize,
150}
151
152#[bitfield(u32)]
153#[allow(non_camel_case_types)]
154pub struct SFCTL {
155    #[bits(13)]
156    pub fifo_cref: usize,
157    pub fifo_lp_mode: bool,
158    #[bits(2)]
159    __: usize,
160    pub miso_hs_rd: bool,    
161    pub lfsr_en: bool,
162    pub prefix_en: bool,
163    #[bits(13)]
164    __: usize,
165}
166
167#[bitfield(u32)]
168#[allow(non_camel_case_types)]
169pub struct STAT0 {
170    #[bits(1, access = RO)]
171    pub sadc_rdy: bool,
172    #[bits(1, access = RO)]
173    pub madc_rdy: bool,
174    #[bits(1, access = RO)]
175    pub madc_bgup: bool,
176    #[bits(1, access = RO)]
177    pub ldo_rdy: bool,
178    pub __: bool,
179    #[bits(3, access = RO)]
180    pub pm: usize,
181    #[bits(3, access = RO)]
182    pub ch_idx: usize,
183    #[bits(3, access = RO)]
184    pub sd_idx: usize,
185    #[bits(18)]
186    pub __: usize,    
187}
188
189#[bitfield(u32)]
190#[allow(non_camel_case_types)]
191pub struct FSTAT {
192    #[bits(14, access = RO)]
193    fill_status: usize,
194    #[bits(3)]
195    __: usize,
196    #[bits(1, access = RO)]
197    pub clk_num_err: bool,
198    #[bits(1, access = RO)]
199    pub spi_burst_err: bool,
200    #[bits(1, access = RO)]
201    pub fuf_err: bool,
202    #[bits(1, access = RO)]
203    pub empty: bool,
204    #[bits(1, access = RO)]
205    pub cref: bool,
206    #[bits(1, access = RO)]
207    pub full: bool,
208    #[bits(1, access = RO)]
209    pub fof_err: bool,
210    #[bits(8)]
211    __: usize,
212}
213
214#[bitfield(u32)]
215#[allow(non_camel_case_types)]
216pub struct BURST {  
217    #[bits(9)]
218    __: usize,
219    #[bits(7)]
220    pub nbursts: usize,
221    #[bits(1)]
222    pub rwb: bool,
223    #[bits(7)]
224    pub saddr: usize,
225    #[bits(1, default = true)]
226    pub rw: bool,
227    #[bits(7, default = 0x7F)]
228    pub addr: usize,
229}
230
231#[bitfield(u8)]
232#[allow(non_camel_case_types)]
233pub struct GSR0 {
234    #[bits(1, access = RO)]
235    pub clock_number_error: bool,
236    #[bits(1, access = RO)]
237    pub spi_burst_error: bool,
238    #[bits(1, access = RO)]
239    pub miso_hs_read: bool,
240    #[bits(1, access = RO)]
241    pub fou_err: bool,
242    #[bits(4)]
243    __: usize,
244}
245
246impl GSR0 {
247    pub fn has_error(&self) -> bool {
248        self.clock_number_error() || self.spi_burst_error() // || self.fou_err() // fou is also set when the FIFO is empty, so we don't check it here, only in the burst read
249    }
250}
bgt60trxx/register.rs

bgt60trxx/
register.rs
