betrusted_pac/
ctrl.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - Write a ``1`` to this register to reset the SoC."]
5    pub reset: RESET,
6    #[doc = "0x04 - Bits 24-31 of `CTRL_SCRATCH`. Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness."]
7    pub scratch3: SCRATCH3,
8    #[doc = "0x08 - Bits 16-23 of `CTRL_SCRATCH`."]
9    pub scratch2: SCRATCH2,
10    #[doc = "0x0c - Bits 8-15 of `CTRL_SCRATCH`."]
11    pub scratch1: SCRATCH1,
12    #[doc = "0x10 - Bits 0-7 of `CTRL_SCRATCH`."]
13    pub scratch0: SCRATCH0,
14    #[doc = "0x14 - Bits 24-31 of `CTRL_BUS_ERRORS`. Total number of Wishbone bus errors (timeouts) since last reset."]
15    pub bus_errors3: BUS_ERRORS3,
16    #[doc = "0x18 - Bits 16-23 of `CTRL_BUS_ERRORS`."]
17    pub bus_errors2: BUS_ERRORS2,
18    #[doc = "0x1c - Bits 8-15 of `CTRL_BUS_ERRORS`."]
19    pub bus_errors1: BUS_ERRORS1,
20    #[doc = "0x20 - Bits 0-7 of `CTRL_BUS_ERRORS`."]
21    pub bus_errors0: BUS_ERRORS0,
22}
23#[doc = "Write a ``1`` to this register to reset the SoC.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset](reset) module"]
24pub type RESET = crate::Reg<u32, _RESET>;
25#[allow(missing_docs)]
26#[doc(hidden)]
27pub struct _RESET;
28#[doc = "`read()` method returns [reset::R](reset::R) reader structure"]
29impl crate::Readable for RESET {}
30#[doc = "`write(|w| ..)` method takes [reset::W](reset::W) writer structure"]
31impl crate::Writable for RESET {}
32#[doc = "Write a ``1`` to this register to reset the SoC."]
33pub mod reset;
34#[doc = "Bits 24-31 of `CTRL_SCRATCH`. Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch3](scratch3) module"]
35pub type SCRATCH3 = crate::Reg<u32, _SCRATCH3>;
36#[allow(missing_docs)]
37#[doc(hidden)]
38pub struct _SCRATCH3;
39#[doc = "`read()` method returns [scratch3::R](scratch3::R) reader structure"]
40impl crate::Readable for SCRATCH3 {}
41#[doc = "`write(|w| ..)` method takes [scratch3::W](scratch3::W) writer structure"]
42impl crate::Writable for SCRATCH3 {}
43#[doc = "Bits 24-31 of `CTRL_SCRATCH`. Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness."]
44pub mod scratch3;
45#[doc = "Bits 16-23 of `CTRL_SCRATCH`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch2](scratch2) module"]
46pub type SCRATCH2 = crate::Reg<u32, _SCRATCH2>;
47#[allow(missing_docs)]
48#[doc(hidden)]
49pub struct _SCRATCH2;
50#[doc = "`read()` method returns [scratch2::R](scratch2::R) reader structure"]
51impl crate::Readable for SCRATCH2 {}
52#[doc = "`write(|w| ..)` method takes [scratch2::W](scratch2::W) writer structure"]
53impl crate::Writable for SCRATCH2 {}
54#[doc = "Bits 16-23 of `CTRL_SCRATCH`."]
55pub mod scratch2;
56#[doc = "Bits 8-15 of `CTRL_SCRATCH`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch1](scratch1) module"]
57pub type SCRATCH1 = crate::Reg<u32, _SCRATCH1>;
58#[allow(missing_docs)]
59#[doc(hidden)]
60pub struct _SCRATCH1;
61#[doc = "`read()` method returns [scratch1::R](scratch1::R) reader structure"]
62impl crate::Readable for SCRATCH1 {}
63#[doc = "`write(|w| ..)` method takes [scratch1::W](scratch1::W) writer structure"]
64impl crate::Writable for SCRATCH1 {}
65#[doc = "Bits 8-15 of `CTRL_SCRATCH`."]
66pub mod scratch1;
67#[doc = "Bits 0-7 of `CTRL_SCRATCH`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch0](scratch0) module"]
68pub type SCRATCH0 = crate::Reg<u32, _SCRATCH0>;
69#[allow(missing_docs)]
70#[doc(hidden)]
71pub struct _SCRATCH0;
72#[doc = "`read()` method returns [scratch0::R](scratch0::R) reader structure"]
73impl crate::Readable for SCRATCH0 {}
74#[doc = "`write(|w| ..)` method takes [scratch0::W](scratch0::W) writer structure"]
75impl crate::Writable for SCRATCH0 {}
76#[doc = "Bits 0-7 of `CTRL_SCRATCH`."]
77pub mod scratch0;
78#[doc = "Bits 24-31 of `CTRL_BUS_ERRORS`. Total number of Wishbone bus errors (timeouts) since last reset.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bus_errors3](bus_errors3) module"]
79pub type BUS_ERRORS3 = crate::Reg<u32, _BUS_ERRORS3>;
80#[allow(missing_docs)]
81#[doc(hidden)]
82pub struct _BUS_ERRORS3;
83#[doc = "`read()` method returns [bus_errors3::R](bus_errors3::R) reader structure"]
84impl crate::Readable for BUS_ERRORS3 {}
85#[doc = "`write(|w| ..)` method takes [bus_errors3::W](bus_errors3::W) writer structure"]
86impl crate::Writable for BUS_ERRORS3 {}
87#[doc = "Bits 24-31 of `CTRL_BUS_ERRORS`. Total number of Wishbone bus errors (timeouts) since last reset."]
88pub mod bus_errors3;
89#[doc = "Bits 16-23 of `CTRL_BUS_ERRORS`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bus_errors2](bus_errors2) module"]
90pub type BUS_ERRORS2 = crate::Reg<u32, _BUS_ERRORS2>;
91#[allow(missing_docs)]
92#[doc(hidden)]
93pub struct _BUS_ERRORS2;
94#[doc = "`read()` method returns [bus_errors2::R](bus_errors2::R) reader structure"]
95impl crate::Readable for BUS_ERRORS2 {}
96#[doc = "`write(|w| ..)` method takes [bus_errors2::W](bus_errors2::W) writer structure"]
97impl crate::Writable for BUS_ERRORS2 {}
98#[doc = "Bits 16-23 of `CTRL_BUS_ERRORS`."]
99pub mod bus_errors2;
100#[doc = "Bits 8-15 of `CTRL_BUS_ERRORS`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bus_errors1](bus_errors1) module"]
101pub type BUS_ERRORS1 = crate::Reg<u32, _BUS_ERRORS1>;
102#[allow(missing_docs)]
103#[doc(hidden)]
104pub struct _BUS_ERRORS1;
105#[doc = "`read()` method returns [bus_errors1::R](bus_errors1::R) reader structure"]
106impl crate::Readable for BUS_ERRORS1 {}
107#[doc = "`write(|w| ..)` method takes [bus_errors1::W](bus_errors1::W) writer structure"]
108impl crate::Writable for BUS_ERRORS1 {}
109#[doc = "Bits 8-15 of `CTRL_BUS_ERRORS`."]
110pub mod bus_errors1;
111#[doc = "Bits 0-7 of `CTRL_BUS_ERRORS`.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bus_errors0](bus_errors0) module"]
112pub type BUS_ERRORS0 = crate::Reg<u32, _BUS_ERRORS0>;
113#[allow(missing_docs)]
114#[doc(hidden)]
115pub struct _BUS_ERRORS0;
116#[doc = "`read()` method returns [bus_errors0::R](bus_errors0::R) reader structure"]
117impl crate::Readable for BUS_ERRORS0 {}
118#[doc = "`write(|w| ..)` method takes [bus_errors0::W](bus_errors0::W) writer structure"]
119impl crate::Writable for BUS_ERRORS0 {}
120#[doc = "Bits 0-7 of `CTRL_BUS_ERRORS`."]
121pub mod bus_errors0;
betrusted_pac/ctrl.rs

betrusted_pac/
ctrl.rs
