1#[doc = "Register `ENABLE_1` reader"]
2pub type R = crate::R<ENABLE_1_SPEC>;
3#[doc = "Register `ENABLE_1` writer"]
4pub type W = crate::W<ENABLE_1_SPEC>;
5#[doc = "Field `TIMER_0` reader - Timer 0"]
6pub type TIMER_0_R = crate::BitReader;
7#[doc = "Field `TIMER_0` writer - Timer 0"]
8pub type TIMER_0_W<'a, REG> = crate::BitWriter1S<'a, REG>;
9#[doc = "Field `TIMER_1` reader - Timer 1"]
10pub type TIMER_1_R = crate::BitReader;
11#[doc = "Field `TIMER_1` writer - Timer 1"]
12pub type TIMER_1_W<'a, REG> = crate::BitWriter1S<'a, REG>;
13#[doc = "Field `TIMER_2` reader - Timer 2"]
14pub type TIMER_2_R = crate::BitReader;
15#[doc = "Field `TIMER_2` writer - Timer 2"]
16pub type TIMER_2_W<'a, REG> = crate::BitWriter1S<'a, REG>;
17#[doc = "Field `TIMER_3` reader - Timer 3"]
18pub type TIMER_3_R = crate::BitReader;
19#[doc = "Field `TIMER_3` writer - Timer 3"]
20pub type TIMER_3_W<'a, REG> = crate::BitWriter1S<'a, REG>;
21#[doc = "Field `H264_0` reader - H264 0"]
22pub type H264_0_R = crate::BitReader;
23#[doc = "Field `H264_0` writer - H264 0"]
24pub type H264_0_W<'a, REG> = crate::BitWriter1S<'a, REG>;
25#[doc = "Field `H264_1` reader - H264 1"]
26pub type H264_1_R = crate::BitReader;
27#[doc = "Field `H264_1` writer - H264 1"]
28pub type H264_1_W<'a, REG> = crate::BitWriter1S<'a, REG>;
29#[doc = "Field `H264_2` reader - H264 2"]
30pub type H264_2_R = crate::BitReader;
31#[doc = "Field `H264_2` writer - H264 2"]
32pub type H264_2_W<'a, REG> = crate::BitWriter1S<'a, REG>;
33#[doc = "Field `JPEG` reader - JPEG"]
34pub type JPEG_R = crate::BitReader;
35#[doc = "Field `JPEG` writer - JPEG"]
36pub type JPEG_W<'a, REG> = crate::BitWriter1S<'a, REG>;
37#[doc = "Field `ISP` reader - ISP"]
38pub type ISP_R = crate::BitReader;
39#[doc = "Field `ISP` writer - ISP"]
40pub type ISP_W<'a, REG> = crate::BitWriter1S<'a, REG>;
41#[doc = "Field `USB` reader - USB"]
42pub type USB_R = crate::BitReader;
43#[doc = "Field `USB` writer - USB"]
44pub type USB_W<'a, REG> = crate::BitWriter1S<'a, REG>;
45#[doc = "Field `V3D` reader - V3D"]
46pub type V3D_R = crate::BitReader;
47#[doc = "Field `V3D` writer - V3D"]
48pub type V3D_W<'a, REG> = crate::BitWriter1S<'a, REG>;
49#[doc = "Field `TRANSPOSER` reader - Transposer"]
50pub type TRANSPOSER_R = crate::BitReader;
51#[doc = "Field `TRANSPOSER` writer - Transposer"]
52pub type TRANSPOSER_W<'a, REG> = crate::BitWriter1S<'a, REG>;
53#[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"]
54pub type MULTICORE_SYNC_0_R = crate::BitReader;
55#[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"]
56pub type MULTICORE_SYNC_0_W<'a, REG> = crate::BitWriter1S<'a, REG>;
57#[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"]
58pub type MULTICORE_SYNC_1_R = crate::BitReader;
59#[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"]
60pub type MULTICORE_SYNC_1_W<'a, REG> = crate::BitWriter1S<'a, REG>;
61#[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"]
62pub type MULTICORE_SYNC_2_R = crate::BitReader;
63#[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"]
64pub type MULTICORE_SYNC_2_W<'a, REG> = crate::BitWriter1S<'a, REG>;
65#[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"]
66pub type MULTICORE_SYNC_3_R = crate::BitReader;
67#[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"]
68pub type MULTICORE_SYNC_3_W<'a, REG> = crate::BitWriter1S<'a, REG>;
69#[doc = "Field `DMA_0` reader - DMA 0"]
70pub type DMA_0_R = crate::BitReader;
71#[doc = "Field `DMA_0` writer - DMA 0"]
72pub type DMA_0_W<'a, REG> = crate::BitWriter1S<'a, REG>;
73#[doc = "Field `DMA_1` reader - DMA 1"]
74pub type DMA_1_R = crate::BitReader;
75#[doc = "Field `DMA_1` writer - DMA 1"]
76pub type DMA_1_W<'a, REG> = crate::BitWriter1S<'a, REG>;
77#[doc = "Field `DMA_2` reader - DMA 2"]
78pub type DMA_2_R = crate::BitReader;
79#[doc = "Field `DMA_2` writer - DMA 2"]
80pub type DMA_2_W<'a, REG> = crate::BitWriter1S<'a, REG>;
81#[doc = "Field `DMA_3` reader - DMA 3"]
82pub type DMA_3_R = crate::BitReader;
83#[doc = "Field `DMA_3` writer - DMA 3"]
84pub type DMA_3_W<'a, REG> = crate::BitWriter1S<'a, REG>;
85#[doc = "Field `DMA_4` reader - DMA 4"]
86pub type DMA_4_R = crate::BitReader;
87#[doc = "Field `DMA_4` writer - DMA 4"]
88pub type DMA_4_W<'a, REG> = crate::BitWriter1S<'a, REG>;
89#[doc = "Field `DMA_5` reader - DMA 5"]
90pub type DMA_5_R = crate::BitReader;
91#[doc = "Field `DMA_5` writer - DMA 5"]
92pub type DMA_5_W<'a, REG> = crate::BitWriter1S<'a, REG>;
93#[doc = "Field `DMA_6` reader - DMA 6"]
94pub type DMA_6_R = crate::BitReader;
95#[doc = "Field `DMA_6` writer - DMA 6"]
96pub type DMA_6_W<'a, REG> = crate::BitWriter1S<'a, REG>;
97#[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"]
98pub type DMA_7_8_R = crate::BitReader;
99#[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"]
100pub type DMA_7_8_W<'a, REG> = crate::BitWriter1S<'a, REG>;
101#[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"]
102pub type DMA_9_10_R = crate::BitReader;
103#[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"]
104pub type DMA_9_10_W<'a, REG> = crate::BitWriter1S<'a, REG>;
105#[doc = "Field `DMA_11` reader - DMA 11"]
106pub type DMA_11_R = crate::BitReader;
107#[doc = "Field `DMA_11` writer - DMA 11"]
108pub type DMA_11_W<'a, REG> = crate::BitWriter1S<'a, REG>;
109#[doc = "Field `DMA_12` reader - DMA 12"]
110pub type DMA_12_R = crate::BitReader;
111#[doc = "Field `DMA_12` writer - DMA 12"]
112pub type DMA_12_W<'a, REG> = crate::BitWriter1S<'a, REG>;
113#[doc = "Field `DMA_13` reader - DMA 13"]
114pub type DMA_13_R = crate::BitReader;
115#[doc = "Field `DMA_13` writer - DMA 13"]
116pub type DMA_13_W<'a, REG> = crate::BitWriter1S<'a, REG>;
117#[doc = "Field `DMA_14` reader - DMA 14"]
118pub type DMA_14_R = crate::BitReader;
119#[doc = "Field `DMA_14` writer - DMA 14"]
120pub type DMA_14_W<'a, REG> = crate::BitWriter1S<'a, REG>;
121#[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"]
122pub type AUX_R = crate::BitReader;
123#[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"]
124pub type AUX_W<'a, REG> = crate::BitWriter1S<'a, REG>;
125#[doc = "Field `ARM` reader - ARM"]
126pub type ARM_R = crate::BitReader;
127#[doc = "Field `ARM` writer - ARM"]
128pub type ARM_W<'a, REG> = crate::BitWriter1S<'a, REG>;
129#[doc = "Field `DMA_15` reader - DMA 15"]
130pub type DMA_15_R = crate::BitReader;
131#[doc = "Field `DMA_15` writer - DMA 15"]
132pub type DMA_15_W<'a, REG> = crate::BitWriter1S<'a, REG>;
133impl R {
134 #[doc = "Bit 0 - Timer 0"]
135 #[inline(always)]
136 pub fn timer_0(&self) -> TIMER_0_R {
137 TIMER_0_R::new((self.bits & 1) != 0)
138 }
139 #[doc = "Bit 1 - Timer 1"]
140 #[inline(always)]
141 pub fn timer_1(&self) -> TIMER_1_R {
142 TIMER_1_R::new(((self.bits >> 1) & 1) != 0)
143 }
144 #[doc = "Bit 2 - Timer 2"]
145 #[inline(always)]
146 pub fn timer_2(&self) -> TIMER_2_R {
147 TIMER_2_R::new(((self.bits >> 2) & 1) != 0)
148 }
149 #[doc = "Bit 3 - Timer 3"]
150 #[inline(always)]
151 pub fn timer_3(&self) -> TIMER_3_R {
152 TIMER_3_R::new(((self.bits >> 3) & 1) != 0)
153 }
154 #[doc = "Bit 4 - H264 0"]
155 #[inline(always)]
156 pub fn h264_0(&self) -> H264_0_R {
157 H264_0_R::new(((self.bits >> 4) & 1) != 0)
158 }
159 #[doc = "Bit 5 - H264 1"]
160 #[inline(always)]
161 pub fn h264_1(&self) -> H264_1_R {
162 H264_1_R::new(((self.bits >> 5) & 1) != 0)
163 }
164 #[doc = "Bit 6 - H264 2"]
165 #[inline(always)]
166 pub fn h264_2(&self) -> H264_2_R {
167 H264_2_R::new(((self.bits >> 6) & 1) != 0)
168 }
169 #[doc = "Bit 7 - JPEG"]
170 #[inline(always)]
171 pub fn jpeg(&self) -> JPEG_R {
172 JPEG_R::new(((self.bits >> 7) & 1) != 0)
173 }
174 #[doc = "Bit 8 - ISP"]
175 #[inline(always)]
176 pub fn isp(&self) -> ISP_R {
177 ISP_R::new(((self.bits >> 8) & 1) != 0)
178 }
179 #[doc = "Bit 9 - USB"]
180 #[inline(always)]
181 pub fn usb(&self) -> USB_R {
182 USB_R::new(((self.bits >> 9) & 1) != 0)
183 }
184 #[doc = "Bit 10 - V3D"]
185 #[inline(always)]
186 pub fn v3d(&self) -> V3D_R {
187 V3D_R::new(((self.bits >> 10) & 1) != 0)
188 }
189 #[doc = "Bit 11 - Transposer"]
190 #[inline(always)]
191 pub fn transposer(&self) -> TRANSPOSER_R {
192 TRANSPOSER_R::new(((self.bits >> 11) & 1) != 0)
193 }
194 #[doc = "Bit 12 - Multicore Sync 0"]
195 #[inline(always)]
196 pub fn multicore_sync_0(&self) -> MULTICORE_SYNC_0_R {
197 MULTICORE_SYNC_0_R::new(((self.bits >> 12) & 1) != 0)
198 }
199 #[doc = "Bit 13 - Multicore Sync 1"]
200 #[inline(always)]
201 pub fn multicore_sync_1(&self) -> MULTICORE_SYNC_1_R {
202 MULTICORE_SYNC_1_R::new(((self.bits >> 13) & 1) != 0)
203 }
204 #[doc = "Bit 14 - Multicore Sync 2"]
205 #[inline(always)]
206 pub fn multicore_sync_2(&self) -> MULTICORE_SYNC_2_R {
207 MULTICORE_SYNC_2_R::new(((self.bits >> 14) & 1) != 0)
208 }
209 #[doc = "Bit 15 - Multicore Sync 3"]
210 #[inline(always)]
211 pub fn multicore_sync_3(&self) -> MULTICORE_SYNC_3_R {
212 MULTICORE_SYNC_3_R::new(((self.bits >> 15) & 1) != 0)
213 }
214 #[doc = "Bit 16 - DMA 0"]
215 #[inline(always)]
216 pub fn dma_0(&self) -> DMA_0_R {
217 DMA_0_R::new(((self.bits >> 16) & 1) != 0)
218 }
219 #[doc = "Bit 17 - DMA 1"]
220 #[inline(always)]
221 pub fn dma_1(&self) -> DMA_1_R {
222 DMA_1_R::new(((self.bits >> 17) & 1) != 0)
223 }
224 #[doc = "Bit 18 - DMA 2"]
225 #[inline(always)]
226 pub fn dma_2(&self) -> DMA_2_R {
227 DMA_2_R::new(((self.bits >> 18) & 1) != 0)
228 }
229 #[doc = "Bit 19 - DMA 3"]
230 #[inline(always)]
231 pub fn dma_3(&self) -> DMA_3_R {
232 DMA_3_R::new(((self.bits >> 19) & 1) != 0)
233 }
234 #[doc = "Bit 20 - DMA 4"]
235 #[inline(always)]
236 pub fn dma_4(&self) -> DMA_4_R {
237 DMA_4_R::new(((self.bits >> 20) & 1) != 0)
238 }
239 #[doc = "Bit 21 - DMA 5"]
240 #[inline(always)]
241 pub fn dma_5(&self) -> DMA_5_R {
242 DMA_5_R::new(((self.bits >> 21) & 1) != 0)
243 }
244 #[doc = "Bit 22 - DMA 6"]
245 #[inline(always)]
246 pub fn dma_6(&self) -> DMA_6_R {
247 DMA_6_R::new(((self.bits >> 22) & 1) != 0)
248 }
249 #[doc = "Bit 23 - OR of DMA 7 and 8"]
250 #[inline(always)]
251 pub fn dma_7_8(&self) -> DMA_7_8_R {
252 DMA_7_8_R::new(((self.bits >> 23) & 1) != 0)
253 }
254 #[doc = "Bit 24 - OR of DMA 9 and 10"]
255 #[inline(always)]
256 pub fn dma_9_10(&self) -> DMA_9_10_R {
257 DMA_9_10_R::new(((self.bits >> 24) & 1) != 0)
258 }
259 #[doc = "Bit 25 - DMA 11"]
260 #[inline(always)]
261 pub fn dma_11(&self) -> DMA_11_R {
262 DMA_11_R::new(((self.bits >> 25) & 1) != 0)
263 }
264 #[doc = "Bit 26 - DMA 12"]
265 #[inline(always)]
266 pub fn dma_12(&self) -> DMA_12_R {
267 DMA_12_R::new(((self.bits >> 26) & 1) != 0)
268 }
269 #[doc = "Bit 27 - DMA 13"]
270 #[inline(always)]
271 pub fn dma_13(&self) -> DMA_13_R {
272 DMA_13_R::new(((self.bits >> 27) & 1) != 0)
273 }
274 #[doc = "Bit 28 - DMA 14"]
275 #[inline(always)]
276 pub fn dma_14(&self) -> DMA_14_R {
277 DMA_14_R::new(((self.bits >> 28) & 1) != 0)
278 }
279 #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"]
280 #[inline(always)]
281 pub fn aux(&self) -> AUX_R {
282 AUX_R::new(((self.bits >> 29) & 1) != 0)
283 }
284 #[doc = "Bit 30 - ARM"]
285 #[inline(always)]
286 pub fn arm(&self) -> ARM_R {
287 ARM_R::new(((self.bits >> 30) & 1) != 0)
288 }
289 #[doc = "Bit 31 - DMA 15"]
290 #[inline(always)]
291 pub fn dma_15(&self) -> DMA_15_R {
292 DMA_15_R::new(((self.bits >> 31) & 1) != 0)
293 }
294}
295impl core::fmt::Debug for R {
296 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
297 f.debug_struct("ENABLE_1")
298 .field("timer_0", &format_args!("{}", self.timer_0().bit()))
299 .field("timer_1", &format_args!("{}", self.timer_1().bit()))
300 .field("timer_2", &format_args!("{}", self.timer_2().bit()))
301 .field("timer_3", &format_args!("{}", self.timer_3().bit()))
302 .field("h264_0", &format_args!("{}", self.h264_0().bit()))
303 .field("h264_1", &format_args!("{}", self.h264_1().bit()))
304 .field("h264_2", &format_args!("{}", self.h264_2().bit()))
305 .field("jpeg", &format_args!("{}", self.jpeg().bit()))
306 .field("isp", &format_args!("{}", self.isp().bit()))
307 .field("usb", &format_args!("{}", self.usb().bit()))
308 .field("v3d", &format_args!("{}", self.v3d().bit()))
309 .field("transposer", &format_args!("{}", self.transposer().bit()))
310 .field(
311 "multicore_sync_0",
312 &format_args!("{}", self.multicore_sync_0().bit()),
313 )
314 .field(
315 "multicore_sync_1",
316 &format_args!("{}", self.multicore_sync_1().bit()),
317 )
318 .field(
319 "multicore_sync_2",
320 &format_args!("{}", self.multicore_sync_2().bit()),
321 )
322 .field(
323 "multicore_sync_3",
324 &format_args!("{}", self.multicore_sync_3().bit()),
325 )
326 .field("dma_0", &format_args!("{}", self.dma_0().bit()))
327 .field("dma_1", &format_args!("{}", self.dma_1().bit()))
328 .field("dma_2", &format_args!("{}", self.dma_2().bit()))
329 .field("dma_3", &format_args!("{}", self.dma_3().bit()))
330 .field("dma_4", &format_args!("{}", self.dma_4().bit()))
331 .field("dma_5", &format_args!("{}", self.dma_5().bit()))
332 .field("dma_6", &format_args!("{}", self.dma_6().bit()))
333 .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit()))
334 .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit()))
335 .field("dma_11", &format_args!("{}", self.dma_11().bit()))
336 .field("dma_12", &format_args!("{}", self.dma_12().bit()))
337 .field("dma_13", &format_args!("{}", self.dma_13().bit()))
338 .field("dma_14", &format_args!("{}", self.dma_14().bit()))
339 .field("aux", &format_args!("{}", self.aux().bit()))
340 .field("arm", &format_args!("{}", self.arm().bit()))
341 .field("dma_15", &format_args!("{}", self.dma_15().bit()))
342 .finish()
343 }
344}
345impl core::fmt::Debug for crate::generic::Reg<ENABLE_1_SPEC> {
346 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
347 core::fmt::Debug::fmt(&self.read(), f)
348 }
349}
350impl W {
351 #[doc = "Bit 0 - Timer 0"]
352 #[inline(always)]
353 #[must_use]
354 pub fn timer_0(&mut self) -> TIMER_0_W<ENABLE_1_SPEC> {
355 TIMER_0_W::new(self, 0)
356 }
357 #[doc = "Bit 1 - Timer 1"]
358 #[inline(always)]
359 #[must_use]
360 pub fn timer_1(&mut self) -> TIMER_1_W<ENABLE_1_SPEC> {
361 TIMER_1_W::new(self, 1)
362 }
363 #[doc = "Bit 2 - Timer 2"]
364 #[inline(always)]
365 #[must_use]
366 pub fn timer_2(&mut self) -> TIMER_2_W<ENABLE_1_SPEC> {
367 TIMER_2_W::new(self, 2)
368 }
369 #[doc = "Bit 3 - Timer 3"]
370 #[inline(always)]
371 #[must_use]
372 pub fn timer_3(&mut self) -> TIMER_3_W<ENABLE_1_SPEC> {
373 TIMER_3_W::new(self, 3)
374 }
375 #[doc = "Bit 4 - H264 0"]
376 #[inline(always)]
377 #[must_use]
378 pub fn h264_0(&mut self) -> H264_0_W<ENABLE_1_SPEC> {
379 H264_0_W::new(self, 4)
380 }
381 #[doc = "Bit 5 - H264 1"]
382 #[inline(always)]
383 #[must_use]
384 pub fn h264_1(&mut self) -> H264_1_W<ENABLE_1_SPEC> {
385 H264_1_W::new(self, 5)
386 }
387 #[doc = "Bit 6 - H264 2"]
388 #[inline(always)]
389 #[must_use]
390 pub fn h264_2(&mut self) -> H264_2_W<ENABLE_1_SPEC> {
391 H264_2_W::new(self, 6)
392 }
393 #[doc = "Bit 7 - JPEG"]
394 #[inline(always)]
395 #[must_use]
396 pub fn jpeg(&mut self) -> JPEG_W<ENABLE_1_SPEC> {
397 JPEG_W::new(self, 7)
398 }
399 #[doc = "Bit 8 - ISP"]
400 #[inline(always)]
401 #[must_use]
402 pub fn isp(&mut self) -> ISP_W<ENABLE_1_SPEC> {
403 ISP_W::new(self, 8)
404 }
405 #[doc = "Bit 9 - USB"]
406 #[inline(always)]
407 #[must_use]
408 pub fn usb(&mut self) -> USB_W<ENABLE_1_SPEC> {
409 USB_W::new(self, 9)
410 }
411 #[doc = "Bit 10 - V3D"]
412 #[inline(always)]
413 #[must_use]
414 pub fn v3d(&mut self) -> V3D_W<ENABLE_1_SPEC> {
415 V3D_W::new(self, 10)
416 }
417 #[doc = "Bit 11 - Transposer"]
418 #[inline(always)]
419 #[must_use]
420 pub fn transposer(&mut self) -> TRANSPOSER_W<ENABLE_1_SPEC> {
421 TRANSPOSER_W::new(self, 11)
422 }
423 #[doc = "Bit 12 - Multicore Sync 0"]
424 #[inline(always)]
425 #[must_use]
426 pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<ENABLE_1_SPEC> {
427 MULTICORE_SYNC_0_W::new(self, 12)
428 }
429 #[doc = "Bit 13 - Multicore Sync 1"]
430 #[inline(always)]
431 #[must_use]
432 pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<ENABLE_1_SPEC> {
433 MULTICORE_SYNC_1_W::new(self, 13)
434 }
435 #[doc = "Bit 14 - Multicore Sync 2"]
436 #[inline(always)]
437 #[must_use]
438 pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<ENABLE_1_SPEC> {
439 MULTICORE_SYNC_2_W::new(self, 14)
440 }
441 #[doc = "Bit 15 - Multicore Sync 3"]
442 #[inline(always)]
443 #[must_use]
444 pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<ENABLE_1_SPEC> {
445 MULTICORE_SYNC_3_W::new(self, 15)
446 }
447 #[doc = "Bit 16 - DMA 0"]
448 #[inline(always)]
449 #[must_use]
450 pub fn dma_0(&mut self) -> DMA_0_W<ENABLE_1_SPEC> {
451 DMA_0_W::new(self, 16)
452 }
453 #[doc = "Bit 17 - DMA 1"]
454 #[inline(always)]
455 #[must_use]
456 pub fn dma_1(&mut self) -> DMA_1_W<ENABLE_1_SPEC> {
457 DMA_1_W::new(self, 17)
458 }
459 #[doc = "Bit 18 - DMA 2"]
460 #[inline(always)]
461 #[must_use]
462 pub fn dma_2(&mut self) -> DMA_2_W<ENABLE_1_SPEC> {
463 DMA_2_W::new(self, 18)
464 }
465 #[doc = "Bit 19 - DMA 3"]
466 #[inline(always)]
467 #[must_use]
468 pub fn dma_3(&mut self) -> DMA_3_W<ENABLE_1_SPEC> {
469 DMA_3_W::new(self, 19)
470 }
471 #[doc = "Bit 20 - DMA 4"]
472 #[inline(always)]
473 #[must_use]
474 pub fn dma_4(&mut self) -> DMA_4_W<ENABLE_1_SPEC> {
475 DMA_4_W::new(self, 20)
476 }
477 #[doc = "Bit 21 - DMA 5"]
478 #[inline(always)]
479 #[must_use]
480 pub fn dma_5(&mut self) -> DMA_5_W<ENABLE_1_SPEC> {
481 DMA_5_W::new(self, 21)
482 }
483 #[doc = "Bit 22 - DMA 6"]
484 #[inline(always)]
485 #[must_use]
486 pub fn dma_6(&mut self) -> DMA_6_W<ENABLE_1_SPEC> {
487 DMA_6_W::new(self, 22)
488 }
489 #[doc = "Bit 23 - OR of DMA 7 and 8"]
490 #[inline(always)]
491 #[must_use]
492 pub fn dma_7_8(&mut self) -> DMA_7_8_W<ENABLE_1_SPEC> {
493 DMA_7_8_W::new(self, 23)
494 }
495 #[doc = "Bit 24 - OR of DMA 9 and 10"]
496 #[inline(always)]
497 #[must_use]
498 pub fn dma_9_10(&mut self) -> DMA_9_10_W<ENABLE_1_SPEC> {
499 DMA_9_10_W::new(self, 24)
500 }
501 #[doc = "Bit 25 - DMA 11"]
502 #[inline(always)]
503 #[must_use]
504 pub fn dma_11(&mut self) -> DMA_11_W<ENABLE_1_SPEC> {
505 DMA_11_W::new(self, 25)
506 }
507 #[doc = "Bit 26 - DMA 12"]
508 #[inline(always)]
509 #[must_use]
510 pub fn dma_12(&mut self) -> DMA_12_W<ENABLE_1_SPEC> {
511 DMA_12_W::new(self, 26)
512 }
513 #[doc = "Bit 27 - DMA 13"]
514 #[inline(always)]
515 #[must_use]
516 pub fn dma_13(&mut self) -> DMA_13_W<ENABLE_1_SPEC> {
517 DMA_13_W::new(self, 27)
518 }
519 #[doc = "Bit 28 - DMA 14"]
520 #[inline(always)]
521 #[must_use]
522 pub fn dma_14(&mut self) -> DMA_14_W<ENABLE_1_SPEC> {
523 DMA_14_W::new(self, 28)
524 }
525 #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"]
526 #[inline(always)]
527 #[must_use]
528 pub fn aux(&mut self) -> AUX_W<ENABLE_1_SPEC> {
529 AUX_W::new(self, 29)
530 }
531 #[doc = "Bit 30 - ARM"]
532 #[inline(always)]
533 #[must_use]
534 pub fn arm(&mut self) -> ARM_W<ENABLE_1_SPEC> {
535 ARM_W::new(self, 30)
536 }
537 #[doc = "Bit 31 - DMA 15"]
538 #[inline(always)]
539 #[must_use]
540 pub fn dma_15(&mut self) -> DMA_15_W<ENABLE_1_SPEC> {
541 DMA_15_W::new(self, 31)
542 }
543 #[doc = r" Writes raw bits to the register."]
544 #[doc = r""]
545 #[doc = r" # Safety"]
546 #[doc = r""]
547 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
548 #[inline(always)]
549 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
550 self.bits = bits;
551 self
552 }
553}
554#[doc = "Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
555pub struct ENABLE_1_SPEC;
556impl crate::RegisterSpec for ENABLE_1_SPEC {
557 type Ux = u32;
558}
559#[doc = "`read()` method returns [`enable_1::R`](R) reader structure"]
560impl crate::Readable for ENABLE_1_SPEC {}
561#[doc = "`write(|w| ..)` method takes [`enable_1::W`](W) writer structure"]
562impl crate::Writable for ENABLE_1_SPEC {
563 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
564 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff;
565}
566#[doc = "`reset()` method sets ENABLE_1 to value 0"]
567impl crate::Resettable for ENABLE_1_SPEC {
568 const RESET_VALUE: u32 = 0;
569}