bcm2711_lpa/spi0/
cs.rs

1#[doc = "Register `CS` reader"]
2pub type R = crate::R<CS_SPEC>;
3#[doc = "Register `CS` writer"]
4pub type W = crate::W<CS_SPEC>;
5#[doc = "Field `CS` reader - Chip select"]
6pub type CS_R = crate::FieldReader;
7#[doc = "Field `CS` writer - Chip select"]
8pub type CS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CPHA` reader - Clock phase"]
10pub type CPHA_R = crate::BitReader;
11#[doc = "Field `CPHA` writer - Clock phase"]
12pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CPOL` reader - Clock polarity"]
14pub type CPOL_R = crate::BitReader;
15#[doc = "Field `CPOL` writer - Clock polarity"]
16pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLEAR` reader - Clear the FIFO(s)"]
18pub type CLEAR_R = crate::FieldReader<CLEAR_A>;
19#[doc = "Clear the FIFO(s)\n\nValue on reset: 0"]
20#[cfg_attr(feature = "defmt", derive(defmt::Format))]
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22#[repr(u8)]
23pub enum CLEAR_A {
24    #[doc = "1: `1`"]
25    TX = 1,
26    #[doc = "2: `10`"]
27    RX = 2,
28    #[doc = "3: `11`"]
29    BOTH = 3,
30}
31impl From<CLEAR_A> for u8 {
32    #[inline(always)]
33    fn from(variant: CLEAR_A) -> Self {
34        variant as _
35    }
36}
37impl crate::FieldSpec for CLEAR_A {
38    type Ux = u8;
39}
40impl CLEAR_R {
41    #[doc = "Get enumerated values variant"]
42    #[inline(always)]
43    pub const fn variant(&self) -> Option<CLEAR_A> {
44        match self.bits {
45            1 => Some(CLEAR_A::TX),
46            2 => Some(CLEAR_A::RX),
47            3 => Some(CLEAR_A::BOTH),
48            _ => None,
49        }
50    }
51    #[doc = "`1`"]
52    #[inline(always)]
53    pub fn is_tx(&self) -> bool {
54        *self == CLEAR_A::TX
55    }
56    #[doc = "`10`"]
57    #[inline(always)]
58    pub fn is_rx(&self) -> bool {
59        *self == CLEAR_A::RX
60    }
61    #[doc = "`11`"]
62    #[inline(always)]
63    pub fn is_both(&self) -> bool {
64        *self == CLEAR_A::BOTH
65    }
66}
67#[doc = "Field `CLEAR` writer - Clear the FIFO(s)"]
68pub type CLEAR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CLEAR_A>;
69impl<'a, REG> CLEAR_W<'a, REG>
70where
71    REG: crate::Writable + crate::RegisterSpec,
72    REG::Ux: From<u8>,
73{
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn tx(self) -> &'a mut crate::W<REG> {
77        self.variant(CLEAR_A::TX)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn rx(self) -> &'a mut crate::W<REG> {
82        self.variant(CLEAR_A::RX)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn both(self) -> &'a mut crate::W<REG> {
87        self.variant(CLEAR_A::BOTH)
88    }
89}
90#[doc = "Field `CSPOL` reader - Chip select polarity"]
91pub type CSPOL_R = crate::BitReader;
92#[doc = "Field `CSPOL` writer - Chip select polarity"]
93pub type CSPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
94#[doc = "Field `TA` reader - Transfer active"]
95pub type TA_R = crate::BitReader;
96#[doc = "Field `TA` writer - Transfer active"]
97pub type TA_W<'a, REG> = crate::BitWriter<'a, REG>;
98#[doc = "Field `DMAEN` reader - Enable DMA"]
99pub type DMAEN_R = crate::BitReader;
100#[doc = "Field `DMAEN` writer - Enable DMA"]
101pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
102#[doc = "Field `INTD` reader - Interrupt on done"]
103pub type INTD_R = crate::BitReader;
104#[doc = "Field `INTD` writer - Interrupt on done"]
105pub type INTD_W<'a, REG> = crate::BitWriter<'a, REG>;
106#[doc = "Field `INTR` reader - Interrupt on RX"]
107pub type INTR_R = crate::BitReader;
108#[doc = "Field `INTR` writer - Interrupt on RX"]
109pub type INTR_W<'a, REG> = crate::BitWriter<'a, REG>;
110#[doc = "Field `ADCS` reader - Automatically deassert chip select"]
111pub type ADCS_R = crate::BitReader;
112#[doc = "Field `ADCS` writer - Automatically deassert chip select"]
113pub type ADCS_W<'a, REG> = crate::BitWriter<'a, REG>;
114#[doc = "Field `REN` reader - Read enable"]
115pub type REN_R = crate::BitReader;
116#[doc = "Field `REN` writer - Read enable"]
117pub type REN_W<'a, REG> = crate::BitWriter<'a, REG>;
118#[doc = "Field `LEN` reader - LoSSI enable"]
119pub type LEN_R = crate::BitReader;
120#[doc = "Field `LEN` writer - LoSSI enable"]
121pub type LEN_W<'a, REG> = crate::BitWriter<'a, REG>;
122#[doc = "Field `LMONO` reader - "]
123pub type LMONO_R = crate::BitReader;
124#[doc = "Field `LMONO` writer - "]
125pub type LMONO_W<'a, REG> = crate::BitWriter<'a, REG>;
126#[doc = "Field `TE_EN` reader - "]
127pub type TE_EN_R = crate::BitReader;
128#[doc = "Field `TE_EN` writer - "]
129pub type TE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
130#[doc = "Field `DONE` reader - Transfer is done"]
131pub type DONE_R = crate::BitReader;
132#[doc = "Field `RXD` reader - RX FIFO contains data"]
133pub type RXD_R = crate::BitReader;
134#[doc = "Field `TXD` reader - TX FIFO can accept data"]
135pub type TXD_R = crate::BitReader;
136#[doc = "Field `RXR` reader - RX FIFO has data to be read"]
137pub type RXR_R = crate::BitReader;
138#[doc = "Field `RXF` reader - RX FIFO full"]
139pub type RXF_R = crate::BitReader;
140#[doc = "Field `CSPOL0` reader - Chip select 0 polarity"]
141pub type CSPOL0_R = crate::BitReader;
142#[doc = "Field `CSPOL0` writer - Chip select 0 polarity"]
143pub type CSPOL0_W<'a, REG> = crate::BitWriter<'a, REG>;
144#[doc = "Field `CSPOL1` reader - Chip select 1 polarity"]
145pub type CSPOL1_R = crate::BitReader;
146#[doc = "Field `CSPOL1` writer - Chip select 1 polarity"]
147pub type CSPOL1_W<'a, REG> = crate::BitWriter<'a, REG>;
148#[doc = "Field `CSPOL2` reader - Chip select 2 polarity"]
149pub type CSPOL2_R = crate::BitReader;
150#[doc = "Field `CSPOL2` writer - Chip select 2 polarity"]
151pub type CSPOL2_W<'a, REG> = crate::BitWriter<'a, REG>;
152#[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"]
153pub type DMA_LEN_R = crate::BitReader;
154#[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"]
155pub type DMA_LEN_W<'a, REG> = crate::BitWriter<'a, REG>;
156#[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"]
157pub type LEN_LONG_R = crate::BitReader;
158#[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"]
159pub type LEN_LONG_W<'a, REG> = crate::BitWriter<'a, REG>;
160impl R {
161    #[doc = "Bits 0:1 - Chip select"]
162    #[inline(always)]
163    pub fn cs(&self) -> CS_R {
164        CS_R::new((self.bits & 3) as u8)
165    }
166    #[doc = "Bit 2 - Clock phase"]
167    #[inline(always)]
168    pub fn cpha(&self) -> CPHA_R {
169        CPHA_R::new(((self.bits >> 2) & 1) != 0)
170    }
171    #[doc = "Bit 3 - Clock polarity"]
172    #[inline(always)]
173    pub fn cpol(&self) -> CPOL_R {
174        CPOL_R::new(((self.bits >> 3) & 1) != 0)
175    }
176    #[doc = "Bits 4:5 - Clear the FIFO(s)"]
177    #[inline(always)]
178    pub fn clear(&self) -> CLEAR_R {
179        CLEAR_R::new(((self.bits >> 4) & 3) as u8)
180    }
181    #[doc = "Bit 6 - Chip select polarity"]
182    #[inline(always)]
183    pub fn cspol(&self) -> CSPOL_R {
184        CSPOL_R::new(((self.bits >> 6) & 1) != 0)
185    }
186    #[doc = "Bit 7 - Transfer active"]
187    #[inline(always)]
188    pub fn ta(&self) -> TA_R {
189        TA_R::new(((self.bits >> 7) & 1) != 0)
190    }
191    #[doc = "Bit 8 - Enable DMA"]
192    #[inline(always)]
193    pub fn dmaen(&self) -> DMAEN_R {
194        DMAEN_R::new(((self.bits >> 8) & 1) != 0)
195    }
196    #[doc = "Bit 9 - Interrupt on done"]
197    #[inline(always)]
198    pub fn intd(&self) -> INTD_R {
199        INTD_R::new(((self.bits >> 9) & 1) != 0)
200    }
201    #[doc = "Bit 10 - Interrupt on RX"]
202    #[inline(always)]
203    pub fn intr(&self) -> INTR_R {
204        INTR_R::new(((self.bits >> 10) & 1) != 0)
205    }
206    #[doc = "Bit 11 - Automatically deassert chip select"]
207    #[inline(always)]
208    pub fn adcs(&self) -> ADCS_R {
209        ADCS_R::new(((self.bits >> 11) & 1) != 0)
210    }
211    #[doc = "Bit 12 - Read enable"]
212    #[inline(always)]
213    pub fn ren(&self) -> REN_R {
214        REN_R::new(((self.bits >> 12) & 1) != 0)
215    }
216    #[doc = "Bit 13 - LoSSI enable"]
217    #[inline(always)]
218    pub fn len(&self) -> LEN_R {
219        LEN_R::new(((self.bits >> 13) & 1) != 0)
220    }
221    #[doc = "Bit 14"]
222    #[inline(always)]
223    pub fn lmono(&self) -> LMONO_R {
224        LMONO_R::new(((self.bits >> 14) & 1) != 0)
225    }
226    #[doc = "Bit 15"]
227    #[inline(always)]
228    pub fn te_en(&self) -> TE_EN_R {
229        TE_EN_R::new(((self.bits >> 15) & 1) != 0)
230    }
231    #[doc = "Bit 16 - Transfer is done"]
232    #[inline(always)]
233    pub fn done(&self) -> DONE_R {
234        DONE_R::new(((self.bits >> 16) & 1) != 0)
235    }
236    #[doc = "Bit 17 - RX FIFO contains data"]
237    #[inline(always)]
238    pub fn rxd(&self) -> RXD_R {
239        RXD_R::new(((self.bits >> 17) & 1) != 0)
240    }
241    #[doc = "Bit 18 - TX FIFO can accept data"]
242    #[inline(always)]
243    pub fn txd(&self) -> TXD_R {
244        TXD_R::new(((self.bits >> 18) & 1) != 0)
245    }
246    #[doc = "Bit 19 - RX FIFO has data to be read"]
247    #[inline(always)]
248    pub fn rxr(&self) -> RXR_R {
249        RXR_R::new(((self.bits >> 19) & 1) != 0)
250    }
251    #[doc = "Bit 20 - RX FIFO full"]
252    #[inline(always)]
253    pub fn rxf(&self) -> RXF_R {
254        RXF_R::new(((self.bits >> 20) & 1) != 0)
255    }
256    #[doc = "Bit 21 - Chip select 0 polarity"]
257    #[inline(always)]
258    pub fn cspol0(&self) -> CSPOL0_R {
259        CSPOL0_R::new(((self.bits >> 21) & 1) != 0)
260    }
261    #[doc = "Bit 22 - Chip select 1 polarity"]
262    #[inline(always)]
263    pub fn cspol1(&self) -> CSPOL1_R {
264        CSPOL1_R::new(((self.bits >> 22) & 1) != 0)
265    }
266    #[doc = "Bit 23 - Chip select 2 polarity"]
267    #[inline(always)]
268    pub fn cspol2(&self) -> CSPOL2_R {
269        CSPOL2_R::new(((self.bits >> 23) & 1) != 0)
270    }
271    #[doc = "Bit 24 - Enable DMA in LoSSI mode"]
272    #[inline(always)]
273    pub fn dma_len(&self) -> DMA_LEN_R {
274        DMA_LEN_R::new(((self.bits >> 24) & 1) != 0)
275    }
276    #[doc = "Bit 25 - Enable long data word in LoSSI mode"]
277    #[inline(always)]
278    pub fn len_long(&self) -> LEN_LONG_R {
279        LEN_LONG_R::new(((self.bits >> 25) & 1) != 0)
280    }
281}
282impl core::fmt::Debug for R {
283    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
284        f.debug_struct("CS")
285            .field("len_long", &format_args!("{}", self.len_long().bit()))
286            .field("dma_len", &format_args!("{}", self.dma_len().bit()))
287            .field("cspol2", &format_args!("{}", self.cspol2().bit()))
288            .field("cspol1", &format_args!("{}", self.cspol1().bit()))
289            .field("cspol0", &format_args!("{}", self.cspol0().bit()))
290            .field("rxf", &format_args!("{}", self.rxf().bit()))
291            .field("rxr", &format_args!("{}", self.rxr().bit()))
292            .field("txd", &format_args!("{}", self.txd().bit()))
293            .field("rxd", &format_args!("{}", self.rxd().bit()))
294            .field("done", &format_args!("{}", self.done().bit()))
295            .field("te_en", &format_args!("{}", self.te_en().bit()))
296            .field("lmono", &format_args!("{}", self.lmono().bit()))
297            .field("len", &format_args!("{}", self.len().bit()))
298            .field("ren", &format_args!("{}", self.ren().bit()))
299            .field("adcs", &format_args!("{}", self.adcs().bit()))
300            .field("intr", &format_args!("{}", self.intr().bit()))
301            .field("intd", &format_args!("{}", self.intd().bit()))
302            .field("dmaen", &format_args!("{}", self.dmaen().bit()))
303            .field("ta", &format_args!("{}", self.ta().bit()))
304            .field("cspol", &format_args!("{}", self.cspol().bit()))
305            .field("clear", &format_args!("{}", self.clear().bits()))
306            .field("cpol", &format_args!("{}", self.cpol().bit()))
307            .field("cpha", &format_args!("{}", self.cpha().bit()))
308            .field("cs", &format_args!("{}", self.cs().bits()))
309            .finish()
310    }
311}
312impl core::fmt::Debug for crate::generic::Reg<CS_SPEC> {
313    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
314        core::fmt::Debug::fmt(&self.read(), f)
315    }
316}
317impl W {
318    #[doc = "Bits 0:1 - Chip select"]
319    #[inline(always)]
320    #[must_use]
321    pub fn cs(&mut self) -> CS_W<CS_SPEC> {
322        CS_W::new(self, 0)
323    }
324    #[doc = "Bit 2 - Clock phase"]
325    #[inline(always)]
326    #[must_use]
327    pub fn cpha(&mut self) -> CPHA_W<CS_SPEC> {
328        CPHA_W::new(self, 2)
329    }
330    #[doc = "Bit 3 - Clock polarity"]
331    #[inline(always)]
332    #[must_use]
333    pub fn cpol(&mut self) -> CPOL_W<CS_SPEC> {
334        CPOL_W::new(self, 3)
335    }
336    #[doc = "Bits 4:5 - Clear the FIFO(s)"]
337    #[inline(always)]
338    #[must_use]
339    pub fn clear(&mut self) -> CLEAR_W<CS_SPEC> {
340        CLEAR_W::new(self, 4)
341    }
342    #[doc = "Bit 6 - Chip select polarity"]
343    #[inline(always)]
344    #[must_use]
345    pub fn cspol(&mut self) -> CSPOL_W<CS_SPEC> {
346        CSPOL_W::new(self, 6)
347    }
348    #[doc = "Bit 7 - Transfer active"]
349    #[inline(always)]
350    #[must_use]
351    pub fn ta(&mut self) -> TA_W<CS_SPEC> {
352        TA_W::new(self, 7)
353    }
354    #[doc = "Bit 8 - Enable DMA"]
355    #[inline(always)]
356    #[must_use]
357    pub fn dmaen(&mut self) -> DMAEN_W<CS_SPEC> {
358        DMAEN_W::new(self, 8)
359    }
360    #[doc = "Bit 9 - Interrupt on done"]
361    #[inline(always)]
362    #[must_use]
363    pub fn intd(&mut self) -> INTD_W<CS_SPEC> {
364        INTD_W::new(self, 9)
365    }
366    #[doc = "Bit 10 - Interrupt on RX"]
367    #[inline(always)]
368    #[must_use]
369    pub fn intr(&mut self) -> INTR_W<CS_SPEC> {
370        INTR_W::new(self, 10)
371    }
372    #[doc = "Bit 11 - Automatically deassert chip select"]
373    #[inline(always)]
374    #[must_use]
375    pub fn adcs(&mut self) -> ADCS_W<CS_SPEC> {
376        ADCS_W::new(self, 11)
377    }
378    #[doc = "Bit 12 - Read enable"]
379    #[inline(always)]
380    #[must_use]
381    pub fn ren(&mut self) -> REN_W<CS_SPEC> {
382        REN_W::new(self, 12)
383    }
384    #[doc = "Bit 13 - LoSSI enable"]
385    #[inline(always)]
386    #[must_use]
387    pub fn len(&mut self) -> LEN_W<CS_SPEC> {
388        LEN_W::new(self, 13)
389    }
390    #[doc = "Bit 14"]
391    #[inline(always)]
392    #[must_use]
393    pub fn lmono(&mut self) -> LMONO_W<CS_SPEC> {
394        LMONO_W::new(self, 14)
395    }
396    #[doc = "Bit 15"]
397    #[inline(always)]
398    #[must_use]
399    pub fn te_en(&mut self) -> TE_EN_W<CS_SPEC> {
400        TE_EN_W::new(self, 15)
401    }
402    #[doc = "Bit 21 - Chip select 0 polarity"]
403    #[inline(always)]
404    #[must_use]
405    pub fn cspol0(&mut self) -> CSPOL0_W<CS_SPEC> {
406        CSPOL0_W::new(self, 21)
407    }
408    #[doc = "Bit 22 - Chip select 1 polarity"]
409    #[inline(always)]
410    #[must_use]
411    pub fn cspol1(&mut self) -> CSPOL1_W<CS_SPEC> {
412        CSPOL1_W::new(self, 22)
413    }
414    #[doc = "Bit 23 - Chip select 2 polarity"]
415    #[inline(always)]
416    #[must_use]
417    pub fn cspol2(&mut self) -> CSPOL2_W<CS_SPEC> {
418        CSPOL2_W::new(self, 23)
419    }
420    #[doc = "Bit 24 - Enable DMA in LoSSI mode"]
421    #[inline(always)]
422    #[must_use]
423    pub fn dma_len(&mut self) -> DMA_LEN_W<CS_SPEC> {
424        DMA_LEN_W::new(self, 24)
425    }
426    #[doc = "Bit 25 - Enable long data word in LoSSI mode"]
427    #[inline(always)]
428    #[must_use]
429    pub fn len_long(&mut self) -> LEN_LONG_W<CS_SPEC> {
430        LEN_LONG_W::new(self, 25)
431    }
432    #[doc = r" Writes raw bits to the register."]
433    #[doc = r""]
434    #[doc = r" # Safety"]
435    #[doc = r""]
436    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
437    #[inline(always)]
438    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
439        self.bits = bits;
440        self
441    }
442}
443#[doc = "Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
444pub struct CS_SPEC;
445impl crate::RegisterSpec for CS_SPEC {
446    type Ux = u32;
447}
448#[doc = "`read()` method returns [`cs::R`](R) reader structure"]
449impl crate::Readable for CS_SPEC {}
450#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
451impl crate::Writable for CS_SPEC {
452    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
453    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
454}
455#[doc = "`reset()` method sets CS to value 0x0004_1000"]
456impl crate::Resettable for CS_SPEC {
457    const RESET_VALUE: u32 = 0x0004_1000;
458}
bcm2711_lpa/spi0/cs.rs

bcm2711_lpa/spi0/
cs.rs
