axi_uartlite/
registers.rs

1//! # Raw register module
2
3/// RX FIFO register.
4#[bitbybit::bitfield(u32)]
5pub struct RxFifo {
6    /// Data which can be read.
7    #[bits(0..=7, r)]
8    pub data: u8,
9}
10
11/// TX FIFO register.
12#[bitbybit::bitfield(u32)]
13pub struct TxFifo {
14    /// Data to be transmitted.
15    #[bits(0..=7, w)]
16    pub data: u8,
17}
18
19/// Status register.
20#[bitbybit::bitfield(u32)]
21pub struct Status {
22    /// Parity error bit.
23    #[bit(7, r)]
24    pub parity_error: bool,
25    /// Frame error bit.
26    #[bit(6, r)]
27    pub frame_error: bool,
28    /// Overrun error bit.
29    #[bit(5, r)]
30    pub overrun_error: bool,
31    /// Interrupt enabled bit.
32    #[bit(4, r)]
33    pub intr_enabled: bool,
34    /// TX FIFO full.
35    #[bit(3, r)]
36    pub tx_fifo_full: bool,
37    /// TX FIFO empty.
38    #[bit(2, r)]
39    pub tx_fifo_empty: bool,
40    /// RX FIFO full.
41    #[bit(1, r)]
42    pub rx_fifo_full: bool,
43    /// RX FIFO contains valid data.
44    #[bit(0, r)]
45    pub rx_fifo_valid_data: bool,
46}
47
48/// Control register.
49#[bitbybit::bitfield(u32, default = 0x0)]
50pub struct Control {
51    /// Enable interrupt bit.
52    #[bit(4, w)]
53    enable_interrupt: bool,
54    /// Reset RX FIFO.
55    #[bit(1, w)]
56    reset_rx_fifo: bool,
57    /// Reset TX FIFO.
58    #[bit(0, w)]
59    reset_tx_fifo: bool,
60}
61
62/// AXI UARTLITE register block definition.
63#[derive(derive_mmio::Mmio)]
64#[repr(C)]
65pub struct Registers {
66    #[mmio(PureRead)]
67    rx_fifo: RxFifo,
68    tx_fifo: TxFifo,
69    #[mmio(PureRead)]
70    stat_reg: Status,
71    ctrl_reg: Control,
72}
axi_uartlite/registers.rs

axi_uartlite/
registers.rs
