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ax_cpu/arch/aarch64/paging/
mod.rs

1//! AArch64 translation formats.
2
3mod stage1;
4mod stage2;
5
6pub(crate) use stage1::{ADDRESS_BITS, LEVEL_BITS, MAX_BLOCK_LEVEL, PAGE_SIZE};
7pub use stage1::{DescriptorFlags, El1Pte, El2Pte, Pte, Stage1Pte, Stage1Regime};
8pub use stage2::Stage2Pte;
9
10/// Four-level, 4-KiB non-VHE EL2 stage-one table geometry.
11#[derive(Clone, Copy)]
12pub struct El2PagingMeta;
13
14impl crate::paging::TableMeta for El2PagingMeta {
15    type P = El2Pte;
16    const PAGE_SIZE: usize = PAGE_SIZE;
17    const LEVEL_BITS: &'static [usize] = LEVEL_BITS;
18    const MAX_BLOCK_LEVEL: usize = MAX_BLOCK_LEVEL;
19
20    fn canonicalize_vaddr(address: crate::VirtAddr) -> crate::VirtAddr {
21        crate::VirtAddr::from_usize(address.as_usize() & ((1usize << ADDRESS_BITS) - 1))
22    }
23
24    fn flush(address: Option<crate::VirtAddr>) {
25        super::mmu::El2::flush_tlb(address);
26    }
27}