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ax_cpu/arch/x86_64/
timer.rs

1//! CPU timestamp counter; frequency and cross-CPU calibration belong to the platform.
2
3/// Reads the raw TSC without instruction serialization.
4/// This alone does not prove counter frequency, invariance or CPU synchronization.
5#[inline]
6pub fn read_counter() -> u64 {
7    // SAFETY: the kernel has access to the timestamp counter. RDTSC changes
8    // no memory or control state and does not require a runtime allocation.
9    unsafe { x86::time::rdtsc() }
10}
11
12/// Reads this CPU's firmware/OS TSC adjustment. CPUID must advertise TSC_ADJUST.
13///
14/// # Safety
15/// Execute at CPL0 on a CPU that implements IA32_TSC_ADJUST.
16pub unsafe fn read_adjustment() -> u64 {
17    // SAFETY: the caller checked CPUID and executes in the owning kernel.
18    unsafe { x86::msr::rdmsr(x86::msr::IA32_TSC_ADJUST) }
19}