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ax_cpu/arch/x86_64/paging/
mod.rs

1//! Native and nested x86 paging formats.
2
3mod ept;
4mod native;
5
6pub use ept::{EptEntry, EptFlags, EptMemoryType};
7pub use native::{DescriptorFlags, Pte};
8pub(crate) use native::{LEVEL_BITS, MAX_BLOCK_LEVEL, PAGE_SIZE};
9
10/// AMD nested paging uses the native long-mode descriptor bit layout.
11/// Its root, ASID ownership and invalidation belong to SVM, not the host CR3.
12pub type NptEntry = Pte;