awr2544_pac/mss_ctrl/
mss_periph_erragg_mask0.rs

1#[doc = "Register `MSS_PERIPH_ERRAGG_MASK0` reader"]
2pub type R = crate::R<MssPeriphErraggMask0Spec>;
3#[doc = "Register `MSS_PERIPH_ERRAGG_MASK0` writer"]
4pub type W = crate::W<MssPeriphErraggMask0Spec>;
5#[doc = "Field `mss_ctrl_rd` reader - 0:0\\]
6Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
7pub type MssCtrlRdR = crate::BitReader;
8#[doc = "Field `mss_ctrl_rd` writer - 0:0\\]
9Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
10pub type MssCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `mss_ctrl_wr` reader - 1:1\\]
12Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
13pub type MssCtrlWrR = crate::BitReader;
14#[doc = "Field `mss_ctrl_wr` writer - 1:1\\]
15Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
16pub type MssCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `mss_rcm_rd` reader - 2:2\\]
18Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
19pub type MssRcmRdR = crate::BitReader;
20#[doc = "Field `mss_rcm_rd` writer - 2:2\\]
21Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
22pub type MssRcmRdW<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `mss_rcm_wr` reader - 3:3\\]
24Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
25pub type MssRcmWrR = crate::BitReader;
26#[doc = "Field `mss_rcm_wr` writer - 3:3\\]
27Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
28pub type MssRcmWrW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `top_ctrl_rd` reader - 4:4\\]
30Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
31pub type TopCtrlRdR = crate::BitReader;
32#[doc = "Field `top_ctrl_rd` writer - 4:4\\]
33Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
34pub type TopCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `top_ctrl_wr` reader - 5:5\\]
36Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
37pub type TopCtrlWrR = crate::BitReader;
38#[doc = "Field `top_ctrl_wr` writer - 5:5\\]
39Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
40pub type TopCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `top_rcm_rd` reader - 6:6\\]
42Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
43pub type TopRcmRdR = crate::BitReader;
44#[doc = "Field `top_rcm_rd` writer - 6:6\\]
45Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
46pub type TopRcmRdW<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `top_rcm_wr` reader - 7:7\\]
48Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
49pub type TopRcmWrR = crate::BitReader;
50#[doc = "Field `top_rcm_wr` writer - 7:7\\]
51Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
52pub type TopRcmWrW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `top_aurora_rd` reader - 8:8\\]
54RESERVED:Dont Use"]
55pub type TopAuroraRdR = crate::BitReader;
56#[doc = "Field `top_aurora_rd` writer - 8:8\\]
57RESERVED:Dont Use"]
58pub type TopAuroraRdW<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `top_aurora_wr` reader - 9:9\\]
60RESERVED:Dont Use"]
61pub type TopAuroraWrR = crate::BitReader;
62#[doc = "Field `top_aurora_wr` writer - 9:9\\]
63RESERVED:Dont Use"]
64pub type TopAuroraWrW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `hsm_soc_ctrl_rd` reader - 10:10\\]
66Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
67pub type HsmSocCtrlRdR = crate::BitReader;
68#[doc = "Field `hsm_soc_ctrl_rd` writer - 10:10\\]
69Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
70pub type HsmSocCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
71#[doc = "Field `hsm_soc_ctrl_wr` reader - 11:11\\]
72Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
73pub type HsmSocCtrlWrR = crate::BitReader;
74#[doc = "Field `hsm_soc_ctrl_wr` writer - 11:11\\]
75Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
76pub type HsmSocCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `hsm_ctrl_rd` reader - 12:12\\]
78Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
79pub type HsmCtrlRdR = crate::BitReader;
80#[doc = "Field `hsm_ctrl_rd` writer - 12:12\\]
81Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
82pub type HsmCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
83#[doc = "Field `hsm_ctrl_wr` reader - 13:13\\]
84Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
85pub type HsmCtrlWrR = crate::BitReader;
86#[doc = "Field `hsm_ctrl_wr` writer - 13:13\\]
87Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
88pub type HsmCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `dss_ctrl_rd` reader - 14:14\\]
90Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
91pub type DssCtrlRdR = crate::BitReader;
92#[doc = "Field `dss_ctrl_rd` writer - 14:14\\]
93Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
94pub type DssCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
95#[doc = "Field `dss_ctrl_wr` reader - 15:15\\]
96Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
97pub type DssCtrlWrR = crate::BitReader;
98#[doc = "Field `dss_ctrl_wr` writer - 15:15\\]
99Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
100pub type DssCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `dss_rcm_rd` reader - 16:16\\]
102Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
103pub type DssRcmRdR = crate::BitReader;
104#[doc = "Field `dss_rcm_rd` writer - 16:16\\]
105Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
106pub type DssRcmRdW<'a, REG> = crate::BitWriter<'a, REG>;
107#[doc = "Field `dss_rcm_wr` reader - 17:17\\]
108Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
109pub type DssRcmWrR = crate::BitReader;
110#[doc = "Field `dss_rcm_wr` writer - 17:17\\]
111Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
112pub type DssRcmWrW<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `dss_cm4_ctrl_rd` reader - 18:18\\]
114RESERVED:Dont Use"]
115pub type DssCm4CtrlRdR = crate::BitReader;
116#[doc = "Field `dss_cm4_ctrl_rd` writer - 18:18\\]
117RESERVED:Dont Use"]
118pub type DssCm4CtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
119#[doc = "Field `dss_cm4_ctrl_wr` reader - 19:19\\]
120RESERVED:Dont Use"]
121pub type DssCm4CtrlWrR = crate::BitReader;
122#[doc = "Field `dss_cm4_ctrl_wr` writer - 19:19\\]
123RESERVED:Dont Use"]
124pub type DssCm4CtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `hwa_cfg_rd` reader - 20:20\\]
126Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
127pub type HwaCfgRdR = crate::BitReader;
128#[doc = "Field `hwa_cfg_rd` writer - 20:20\\]
129Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
130pub type HwaCfgRdW<'a, REG> = crate::BitWriter<'a, REG>;
131#[doc = "Field `hwa_cfg_wr` reader - 21:21\\]
132Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
133pub type HwaCfgWrR = crate::BitReader;
134#[doc = "Field `hwa_cfg_wr` writer - 21:21\\]
135Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
136pub type HwaCfgWrW<'a, REG> = crate::BitWriter<'a, REG>;
137#[doc = "Field `rcss_ctrl_rd` reader - 22:22\\]
138Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
139pub type RcssCtrlRdR = crate::BitReader;
140#[doc = "Field `rcss_ctrl_rd` writer - 22:22\\]
141Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
142pub type RcssCtrlRdW<'a, REG> = crate::BitWriter<'a, REG>;
143#[doc = "Field `rcss_ctrl_wr` reader - 23:23\\]
144Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
145pub type RcssCtrlWrR = crate::BitReader;
146#[doc = "Field `rcss_ctrl_wr` writer - 23:23\\]
147Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
148pub type RcssCtrlWrW<'a, REG> = crate::BitWriter<'a, REG>;
149#[doc = "Field `rcss_rcm_rd` reader - 24:24\\]
150Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
151pub type RcssRcmRdR = crate::BitReader;
152#[doc = "Field `rcss_rcm_rd` writer - 24:24\\]
153Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
154pub type RcssRcmRdW<'a, REG> = crate::BitWriter<'a, REG>;
155#[doc = "Field `rcss_rcm_wr` reader - 25:25\\]
156Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
157pub type RcssRcmWrR = crate::BitReader;
158#[doc = "Field `rcss_rcm_wr` writer - 25:25\\]
159Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
160pub type RcssRcmWrW<'a, REG> = crate::BitWriter<'a, REG>;
161#[doc = "Field `top_mdo_rd` reader - 26:26\\]
162RESERVED:Dont Use"]
163pub type TopMdoRdR = crate::BitReader;
164#[doc = "Field `top_mdo_rd` writer - 26:26\\]
165RESERVED:Dont Use"]
166pub type TopMdoRdW<'a, REG> = crate::BitWriter<'a, REG>;
167#[doc = "Field `top_mdo_wr` reader - 27:27\\]
168RESERVED:Dont Use"]
169pub type TopMdoWrR = crate::BitReader;
170#[doc = "Field `top_mdo_wr` writer - 27:27\\]
171RESERVED:Dont Use"]
172pub type TopMdoWrW<'a, REG> = crate::BitWriter<'a, REG>;
173impl R {
174    #[doc = "Bit 0 - 0:0\\]
175Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
176    #[inline(always)]
177    pub fn mss_ctrl_rd(&self) -> MssCtrlRdR {
178        MssCtrlRdR::new((self.bits & 1) != 0)
179    }
180    #[doc = "Bit 1 - 1:1\\]
181Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
182    #[inline(always)]
183    pub fn mss_ctrl_wr(&self) -> MssCtrlWrR {
184        MssCtrlWrR::new(((self.bits >> 1) & 1) != 0)
185    }
186    #[doc = "Bit 2 - 2:2\\]
187Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
188    #[inline(always)]
189    pub fn mss_rcm_rd(&self) -> MssRcmRdR {
190        MssRcmRdR::new(((self.bits >> 2) & 1) != 0)
191    }
192    #[doc = "Bit 3 - 3:3\\]
193Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
194    #[inline(always)]
195    pub fn mss_rcm_wr(&self) -> MssRcmWrR {
196        MssRcmWrR::new(((self.bits >> 3) & 1) != 0)
197    }
198    #[doc = "Bit 4 - 4:4\\]
199Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
200    #[inline(always)]
201    pub fn top_ctrl_rd(&self) -> TopCtrlRdR {
202        TopCtrlRdR::new(((self.bits >> 4) & 1) != 0)
203    }
204    #[doc = "Bit 5 - 5:5\\]
205Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
206    #[inline(always)]
207    pub fn top_ctrl_wr(&self) -> TopCtrlWrR {
208        TopCtrlWrR::new(((self.bits >> 5) & 1) != 0)
209    }
210    #[doc = "Bit 6 - 6:6\\]
211Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
212    #[inline(always)]
213    pub fn top_rcm_rd(&self) -> TopRcmRdR {
214        TopRcmRdR::new(((self.bits >> 6) & 1) != 0)
215    }
216    #[doc = "Bit 7 - 7:7\\]
217Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
218    #[inline(always)]
219    pub fn top_rcm_wr(&self) -> TopRcmWrR {
220        TopRcmWrR::new(((self.bits >> 7) & 1) != 0)
221    }
222    #[doc = "Bit 8 - 8:8\\]
223RESERVED:Dont Use"]
224    #[inline(always)]
225    pub fn top_aurora_rd(&self) -> TopAuroraRdR {
226        TopAuroraRdR::new(((self.bits >> 8) & 1) != 0)
227    }
228    #[doc = "Bit 9 - 9:9\\]
229RESERVED:Dont Use"]
230    #[inline(always)]
231    pub fn top_aurora_wr(&self) -> TopAuroraWrR {
232        TopAuroraWrR::new(((self.bits >> 9) & 1) != 0)
233    }
234    #[doc = "Bit 10 - 10:10\\]
235Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
236    #[inline(always)]
237    pub fn hsm_soc_ctrl_rd(&self) -> HsmSocCtrlRdR {
238        HsmSocCtrlRdR::new(((self.bits >> 10) & 1) != 0)
239    }
240    #[doc = "Bit 11 - 11:11\\]
241Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
242    #[inline(always)]
243    pub fn hsm_soc_ctrl_wr(&self) -> HsmSocCtrlWrR {
244        HsmSocCtrlWrR::new(((self.bits >> 11) & 1) != 0)
245    }
246    #[doc = "Bit 12 - 12:12\\]
247Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
248    #[inline(always)]
249    pub fn hsm_ctrl_rd(&self) -> HsmCtrlRdR {
250        HsmCtrlRdR::new(((self.bits >> 12) & 1) != 0)
251    }
252    #[doc = "Bit 13 - 13:13\\]
253Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
254    #[inline(always)]
255    pub fn hsm_ctrl_wr(&self) -> HsmCtrlWrR {
256        HsmCtrlWrR::new(((self.bits >> 13) & 1) != 0)
257    }
258    #[doc = "Bit 14 - 14:14\\]
259Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
260    #[inline(always)]
261    pub fn dss_ctrl_rd(&self) -> DssCtrlRdR {
262        DssCtrlRdR::new(((self.bits >> 14) & 1) != 0)
263    }
264    #[doc = "Bit 15 - 15:15\\]
265Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
266    #[inline(always)]
267    pub fn dss_ctrl_wr(&self) -> DssCtrlWrR {
268        DssCtrlWrR::new(((self.bits >> 15) & 1) != 0)
269    }
270    #[doc = "Bit 16 - 16:16\\]
271Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
272    #[inline(always)]
273    pub fn dss_rcm_rd(&self) -> DssRcmRdR {
274        DssRcmRdR::new(((self.bits >> 16) & 1) != 0)
275    }
276    #[doc = "Bit 17 - 17:17\\]
277Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
278    #[inline(always)]
279    pub fn dss_rcm_wr(&self) -> DssRcmWrR {
280        DssRcmWrR::new(((self.bits >> 17) & 1) != 0)
281    }
282    #[doc = "Bit 18 - 18:18\\]
283RESERVED:Dont Use"]
284    #[inline(always)]
285    pub fn dss_cm4_ctrl_rd(&self) -> DssCm4CtrlRdR {
286        DssCm4CtrlRdR::new(((self.bits >> 18) & 1) != 0)
287    }
288    #[doc = "Bit 19 - 19:19\\]
289RESERVED:Dont Use"]
290    #[inline(always)]
291    pub fn dss_cm4_ctrl_wr(&self) -> DssCm4CtrlWrR {
292        DssCm4CtrlWrR::new(((self.bits >> 19) & 1) != 0)
293    }
294    #[doc = "Bit 20 - 20:20\\]
295Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
296    #[inline(always)]
297    pub fn hwa_cfg_rd(&self) -> HwaCfgRdR {
298        HwaCfgRdR::new(((self.bits >> 20) & 1) != 0)
299    }
300    #[doc = "Bit 21 - 21:21\\]
301Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
302    #[inline(always)]
303    pub fn hwa_cfg_wr(&self) -> HwaCfgWrR {
304        HwaCfgWrR::new(((self.bits >> 21) & 1) != 0)
305    }
306    #[doc = "Bit 22 - 22:22\\]
307Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
308    #[inline(always)]
309    pub fn rcss_ctrl_rd(&self) -> RcssCtrlRdR {
310        RcssCtrlRdR::new(((self.bits >> 22) & 1) != 0)
311    }
312    #[doc = "Bit 23 - 23:23\\]
313Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
314    #[inline(always)]
315    pub fn rcss_ctrl_wr(&self) -> RcssCtrlWrR {
316        RcssCtrlWrR::new(((self.bits >> 23) & 1) != 0)
317    }
318    #[doc = "Bit 24 - 24:24\\]
319Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
320    #[inline(always)]
321    pub fn rcss_rcm_rd(&self) -> RcssRcmRdR {
322        RcssRcmRdR::new(((self.bits >> 24) & 1) != 0)
323    }
324    #[doc = "Bit 25 - 25:25\\]
325Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
326    #[inline(always)]
327    pub fn rcss_rcm_wr(&self) -> RcssRcmWrR {
328        RcssRcmWrR::new(((self.bits >> 25) & 1) != 0)
329    }
330    #[doc = "Bit 26 - 26:26\\]
331RESERVED:Dont Use"]
332    #[inline(always)]
333    pub fn top_mdo_rd(&self) -> TopMdoRdR {
334        TopMdoRdR::new(((self.bits >> 26) & 1) != 0)
335    }
336    #[doc = "Bit 27 - 27:27\\]
337RESERVED:Dont Use"]
338    #[inline(always)]
339    pub fn top_mdo_wr(&self) -> TopMdoWrR {
340        TopMdoWrR::new(((self.bits >> 27) & 1) != 0)
341    }
342}
343impl W {
344    #[doc = "Bit 0 - 0:0\\]
345Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
346    #[inline(always)]
347    #[must_use]
348    pub fn mss_ctrl_rd(&mut self) -> MssCtrlRdW<MssPeriphErraggMask0Spec> {
349        MssCtrlRdW::new(self, 0)
350    }
351    #[doc = "Bit 1 - 1:1\\]
352Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
353    #[inline(always)]
354    #[must_use]
355    pub fn mss_ctrl_wr(&mut self) -> MssCtrlWrW<MssPeriphErraggMask0Spec> {
356        MssCtrlWrW::new(self, 1)
357    }
358    #[doc = "Bit 2 - 2:2\\]
359Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
360    #[inline(always)]
361    #[must_use]
362    pub fn mss_rcm_rd(&mut self) -> MssRcmRdW<MssPeriphErraggMask0Spec> {
363        MssRcmRdW::new(self, 2)
364    }
365    #[doc = "Bit 3 - 3:3\\]
366Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
367    #[inline(always)]
368    #[must_use]
369    pub fn mss_rcm_wr(&mut self) -> MssRcmWrW<MssPeriphErraggMask0Spec> {
370        MssRcmWrW::new(self, 3)
371    }
372    #[doc = "Bit 4 - 4:4\\]
373Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
374    #[inline(always)]
375    #[must_use]
376    pub fn top_ctrl_rd(&mut self) -> TopCtrlRdW<MssPeriphErraggMask0Spec> {
377        TopCtrlRdW::new(self, 4)
378    }
379    #[doc = "Bit 5 - 5:5\\]
380Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
381    #[inline(always)]
382    #[must_use]
383    pub fn top_ctrl_wr(&mut self) -> TopCtrlWrW<MssPeriphErraggMask0Spec> {
384        TopCtrlWrW::new(self, 5)
385    }
386    #[doc = "Bit 6 - 6:6\\]
387Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
388    #[inline(always)]
389    #[must_use]
390    pub fn top_rcm_rd(&mut self) -> TopRcmRdW<MssPeriphErraggMask0Spec> {
391        TopRcmRdW::new(self, 6)
392    }
393    #[doc = "Bit 7 - 7:7\\]
394Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
395    #[inline(always)]
396    #[must_use]
397    pub fn top_rcm_wr(&mut self) -> TopRcmWrW<MssPeriphErraggMask0Spec> {
398        TopRcmWrW::new(self, 7)
399    }
400    #[doc = "Bit 8 - 8:8\\]
401RESERVED:Dont Use"]
402    #[inline(always)]
403    #[must_use]
404    pub fn top_aurora_rd(&mut self) -> TopAuroraRdW<MssPeriphErraggMask0Spec> {
405        TopAuroraRdW::new(self, 8)
406    }
407    #[doc = "Bit 9 - 9:9\\]
408RESERVED:Dont Use"]
409    #[inline(always)]
410    #[must_use]
411    pub fn top_aurora_wr(&mut self) -> TopAuroraWrW<MssPeriphErraggMask0Spec> {
412        TopAuroraWrW::new(self, 9)
413    }
414    #[doc = "Bit 10 - 10:10\\]
415Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
416    #[inline(always)]
417    #[must_use]
418    pub fn hsm_soc_ctrl_rd(&mut self) -> HsmSocCtrlRdW<MssPeriphErraggMask0Spec> {
419        HsmSocCtrlRdW::new(self, 10)
420    }
421    #[doc = "Bit 11 - 11:11\\]
422Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
423    #[inline(always)]
424    #[must_use]
425    pub fn hsm_soc_ctrl_wr(&mut self) -> HsmSocCtrlWrW<MssPeriphErraggMask0Spec> {
426        HsmSocCtrlWrW::new(self, 11)
427    }
428    #[doc = "Bit 12 - 12:12\\]
429Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
430    #[inline(always)]
431    #[must_use]
432    pub fn hsm_ctrl_rd(&mut self) -> HsmCtrlRdW<MssPeriphErraggMask0Spec> {
433        HsmCtrlRdW::new(self, 12)
434    }
435    #[doc = "Bit 13 - 13:13\\]
436Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
437    #[inline(always)]
438    #[must_use]
439    pub fn hsm_ctrl_wr(&mut self) -> HsmCtrlWrW<MssPeriphErraggMask0Spec> {
440        HsmCtrlWrW::new(self, 13)
441    }
442    #[doc = "Bit 14 - 14:14\\]
443Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
444    #[inline(always)]
445    #[must_use]
446    pub fn dss_ctrl_rd(&mut self) -> DssCtrlRdW<MssPeriphErraggMask0Spec> {
447        DssCtrlRdW::new(self, 14)
448    }
449    #[doc = "Bit 15 - 15:15\\]
450Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
451    #[inline(always)]
452    #[must_use]
453    pub fn dss_ctrl_wr(&mut self) -> DssCtrlWrW<MssPeriphErraggMask0Spec> {
454        DssCtrlWrW::new(self, 15)
455    }
456    #[doc = "Bit 16 - 16:16\\]
457Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
458    #[inline(always)]
459    #[must_use]
460    pub fn dss_rcm_rd(&mut self) -> DssRcmRdW<MssPeriphErraggMask0Spec> {
461        DssRcmRdW::new(self, 16)
462    }
463    #[doc = "Bit 17 - 17:17\\]
464Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
465    #[inline(always)]
466    #[must_use]
467    pub fn dss_rcm_wr(&mut self) -> DssRcmWrW<MssPeriphErraggMask0Spec> {
468        DssRcmWrW::new(self, 17)
469    }
470    #[doc = "Bit 18 - 18:18\\]
471RESERVED:Dont Use"]
472    #[inline(always)]
473    #[must_use]
474    pub fn dss_cm4_ctrl_rd(&mut self) -> DssCm4CtrlRdW<MssPeriphErraggMask0Spec> {
475        DssCm4CtrlRdW::new(self, 18)
476    }
477    #[doc = "Bit 19 - 19:19\\]
478RESERVED:Dont Use"]
479    #[inline(always)]
480    #[must_use]
481    pub fn dss_cm4_ctrl_wr(&mut self) -> DssCm4CtrlWrW<MssPeriphErraggMask0Spec> {
482        DssCm4CtrlWrW::new(self, 19)
483    }
484    #[doc = "Bit 20 - 20:20\\]
485Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
486    #[inline(always)]
487    #[must_use]
488    pub fn hwa_cfg_rd(&mut self) -> HwaCfgRdW<MssPeriphErraggMask0Spec> {
489        HwaCfgRdW::new(self, 20)
490    }
491    #[doc = "Bit 21 - 21:21\\]
492Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
493    #[inline(always)]
494    #[must_use]
495    pub fn hwa_cfg_wr(&mut self) -> HwaCfgWrW<MssPeriphErraggMask0Spec> {
496        HwaCfgWrW::new(self, 21)
497    }
498    #[doc = "Bit 22 - 22:22\\]
499Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
500    #[inline(always)]
501    #[must_use]
502    pub fn rcss_ctrl_rd(&mut self) -> RcssCtrlRdW<MssPeriphErraggMask0Spec> {
503        RcssCtrlRdW::new(self, 22)
504    }
505    #[doc = "Bit 23 - 23:23\\]
506Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
507    #[inline(always)]
508    #[must_use]
509    pub fn rcss_ctrl_wr(&mut self) -> RcssCtrlWrW<MssPeriphErraggMask0Spec> {
510        RcssCtrlWrW::new(self, 23)
511    }
512    #[doc = "Bit 24 - 24:24\\]
513Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
514    #[inline(always)]
515    #[must_use]
516    pub fn rcss_rcm_rd(&mut self) -> RcssRcmRdW<MssPeriphErraggMask0Spec> {
517        RcssRcmRdW::new(self, 24)
518    }
519    #[doc = "Bit 25 - 25:25\\]
520Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked"]
521    #[inline(always)]
522    #[must_use]
523    pub fn rcss_rcm_wr(&mut self) -> RcssRcmWrW<MssPeriphErraggMask0Spec> {
524        RcssRcmWrW::new(self, 25)
525    }
526    #[doc = "Bit 26 - 26:26\\]
527RESERVED:Dont Use"]
528    #[inline(always)]
529    #[must_use]
530    pub fn top_mdo_rd(&mut self) -> TopMdoRdW<MssPeriphErraggMask0Spec> {
531        TopMdoRdW::new(self, 26)
532    }
533    #[doc = "Bit 27 - 27:27\\]
534RESERVED:Dont Use"]
535    #[inline(always)]
536    #[must_use]
537    pub fn top_mdo_wr(&mut self) -> TopMdoWrW<MssPeriphErraggMask0Spec> {
538        TopMdoWrW::new(self, 27)
539    }
540}
541#[doc = "MSS_PERIPH_ERRAGG_MASK0\n\nYou can [`read`](crate::Reg::read) this register and get [`mss_periph_erragg_mask0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mss_periph_erragg_mask0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
542pub struct MssPeriphErraggMask0Spec;
543impl crate::RegisterSpec for MssPeriphErraggMask0Spec {
544    type Ux = u32;
545}
546#[doc = "`read()` method returns [`mss_periph_erragg_mask0::R`](R) reader structure"]
547impl crate::Readable for MssPeriphErraggMask0Spec {}
548#[doc = "`write(|w| ..)` method takes [`mss_periph_erragg_mask0::W`](W) writer structure"]
549impl crate::Writable for MssPeriphErraggMask0Spec {
550    type Safety = crate::Unsafe;
551    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
552    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
553}
554#[doc = "`reset()` method sets MSS_PERIPH_ERRAGG_MASK0 to value 0"]
555impl crate::Resettable for MssPeriphErraggMask0Spec {
556    const RESET_VALUE: u32 = 0;
557}
awr2544_pac/mss_ctrl/mss_periph_erragg_mask0.rs

awr2544_pac/mss_ctrl/
mss_periph_erragg_mask0.rs
