Module avrd::attiny441

The AVR ATtiny441 microcontroller

Variants

	Pinout	Package	Operating temperature	Operating voltage	Max speed
ATtiny441-SSU	SOIC_14	SOIC14	-40°C - 85°C	1.7V - 5.5V	16 MHz
ATtiny441-MU	QFN_20	MLF20	-40°C - 85°C	1.7V - 5.5V	16 MHz
ATtiny441-MMH	QFN_20	VQFN20	-40°C - 85°C	1.7V - 5.5V	16 MHz

Registers by module (not exhaustive)

PORT modules

• PORTB
  • PB0 (PB0)
  • PB1 (PB1)
  • PB2 (PB2)
  • PB3 (PB3)
• PORTA
  • PA0 (PA0)
  • PA1 (PA1)
  • PA2 (PA2)
  • PA3 (PA3)
  • PA4 (PA4)
  • PA5 (PA5)
  • PA6 (PA6)
  • PA7 (PA7)

USART modules

• USART1
  • PA4 (PA4)
  • PA5 (PA5)
  • PA6 (PA6)
• USART0
  • PA1 (PA1)
  • PA2 (PA2)
  • PA3 (PA3)
  • PA7 (PA7)
  • PB2 (PB2)
  • PA3 (PA3)

ADC modules

• ADC
  • PA0 (PA0)
  • PA1 (PA1)
  • PA2 (PA2)
  • PA3 (PA3)
  • PA4 (PA4)
  • PA5 (PA5)
  • PA6 (PA6)
  • PA7 (PA7)
  • PB2 (PB2)
  • PB3 (PB3)
  • PB0 (PB0)
  • PB1 (PB1)
  • PA0 (PA0)

EEPROM modules

• EEPROM

Constants

ACSR0A	Analog Comparator 0 Control And Status Register A.
ACSR0B	Analog Comparator 0 Control And Status Register B.
ACSR1A	Analog Comparator 1 Control And Status Register A.
ACSR1B	Analog Comparator 1 Control And Status Register B.
ADC	ADC Data Register Bytes.
ADCH	ADC Data Register Bytes high byte.
ADCL	ADC Data Register Bytes low byte.
ADCSRA	The ADC Control and Status register.
ADCSRB	ADC Control and Status Register B.
ADMUXA	The ADC multiplexer Selection Register A.
ADMUXB	The ADC multiplexer Selection Register B.
CCP	Configuration Change Protection.
CLKCR	Clock Control Register.
CLKPR	Clock Prescale Register.
DDRA	Data Direction Register, Port A.
DDRB	Data Direction Register, Port B.
DIDR0	Digital Input Disable Register 0.
DIDR1	Digital Input Disable Register 1.
EEAR	EEPROM Address Register Bytes.
EEARH	EEPROM Address Register Bytes high byte.
EEARL	EEPROM Address Register Bytes low byte.
EECR	EEPROM Control Register.
EEDR	EEPROM Data Register.
EXTENDED
GIFR	General Interrupt Flag register.
GIMSK	General Interrupt Mask Register.
GPIOR0	General Purpose I/O Register 0.
GPIOR1	General Purpose I/O Register 1.
GPIOR2	General Purpose I/O Register 2.
GTCCR	General Timer/Counter Control Register.
HIGH
ICR1	Timer/Counter1 Input Capture Register Bytes.
ICR2	Timer/Counter2 Input Capture Register Bytes.
ICR1H	Timer/Counter1 Input Capture Register Bytes high byte.
ICR1L	Timer/Counter1 Input Capture Register Bytes low byte.
ICR2H	Timer/Counter2 Input Capture Register Bytes high byte.
ICR2L	Timer/Counter2 Input Capture Register Bytes low byte.
LOCKBIT
LOW
MCUCR	MCU Control Register.
MCUSR	MCU Status Register.
OCR0A	Timer/Counter0 Output Compare Register A.
OCR0B	Timer/Counter0 Output Compare Register B.
OCR1A	Timer/Counter1 Output Compare Register A Bytes.
OCR1AH	Timer/Counter1 Output Compare Register A Bytes high byte.
OCR1AL	Timer/Counter1 Output Compare Register A Bytes low byte.
OCR1B	Timer/Counter1 Output Compare Register B Bytes.
OCR1BH	Timer/Counter1 Output Compare Register B Bytes high byte.
OCR1BL	Timer/Counter1 Output Compare Register B Bytes low byte.
OCR2A	Timer/Counter2 Output Compare Register A Bytes.
OCR2AH	Timer/Counter2 Output Compare Register A Bytes high byte.
OCR2AL	Timer/Counter2 Output Compare Register A Bytes low byte.
OCR2B	Timer/Counter2 Output Compare Register B Bytes.
OCR2BH	Timer/Counter2 Output Compare Register B Bytes high byte.
OCR2BL	Timer/Counter2 Output Compare Register B Bytes low byte.
OSCCAL0	Oscillator Calibration Register 8MHz.
OSCCAL1	Oscillator Calibration Register 32kHz.
OSCTCAL0A	Oscillator Temperature Calibration Register A.
OSCTCAL0B	Oscillator Temperature Calibration Register B.
PCMSK0	Pin Change Enable Mask 0.
PCMSK1	Pin Change Enable Mask 1.
PHDE	Port High Drive Enable Register.
PINA	Port A Input Pins.
PINB	Port B Data register.
PORTA	Port A Data Register.
PORTB	Input Pins, Port B.
PORTCR	Port Control Register.
PRR	Power Reduction Register.
PUEA	Pull-up Enable Control Register.
PUEB	Pull-up Enable Control Register.
REMAP	Remap Port Pins.
SP	Stack Pointer.
SPCR	SPI Control Register.
SPDR	SPI Data Register.
SPH	Stack Pointer high byte.
SPL	Stack Pointer low byte.
SPMCSR	Store Program Memory Control and Status Register.
SPSR	SPI Status Register.
SREG	Status Register.
TCCR0A	Timer/Counter Control Register A.
TCCR0B	Timer/Counter Control Register B.
TCCR1A	Timer/Counter1 Control Register A.
TCCR1B	Timer/Counter1 Control Register B.
TCCR1C	Timer/Counter1 Control Register C.
TCCR2A	Timer/Counter2 Control Register A.
TCCR2B	Timer/Counter2 Control Register B.
TCCR2C	Timer/Counter2 Control Register C.
TCNT0	Timer/Counter0.
TCNT1	Timer/Counter1 Bytes.
TCNT2	Timer/Counter2 Bytes.
TCNT1H	Timer/Counter1 Bytes high byte.
TCNT1L	Timer/Counter1 Bytes low byte.
TCNT2H	Timer/Counter2 Bytes high byte.
TCNT2L	Timer/Counter2 Bytes low byte.
TIFR0	Timer/Counter0 Interrupt Flag Register.
TIFR1	Timer/Counter Interrupt Flag register.
TIFR2	Timer/Counter Interrupt Flag register.
TIMSK0	Timer/Counter Interrupt Mask Register.
TIMSK1	Timer/Counter1 Interrupt Mask Register.
TIMSK2	Timer/Counter2 Interrupt Mask Register.
TOCPMCOE	Timer Output Compare Pin Mux Channel Output Enable.
TOCPMSA0	Timer Output Compare Pin Mux Selection 0.
TOCPMSA1	Timer Output Compare Pin Mux Selection 1.
TWSA	TWI Slave Address Register.
TWSAM	TWI Slave Address Mask Register.
TWSCRA	TWI Slave Control Register A.
TWSCRB	TWI Slave Control Register B.
TWSD	TWI Slave Data Register.
TWSSRA	TWI Slave Status Register A.
UBRR0	USART Baud Rate Register Bytes.
UBRR1	USART Baud Rate Register Bytes.
UBRR0H	USART Baud Rate Register Bytes high byte.
UBRR0L	USART Baud Rate Register Bytes low byte.
UBRR1H	USART Baud Rate Register Bytes high byte.
UBRR1L	USART Baud Rate Register Bytes low byte.
UCSR0A	USART Control and Status Register A.
UCSR0B	USART Control and Status Register B.
UCSR0C	USART Control and Status Register C.
UCSR0D	USART Control and Status Register D.
UCSR1A	USART Control and Status Register A.
UCSR1B	USART Control and Status Register B.
UCSR1C	USART Control and Status Register C.
UCSR1D	USART Control and Status Register D.
UDR0	USART I/O Data Register.
UDR1	USART I/O Data Register.
WDTCSR	Watchdog Timer Control and Status Register.