1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311

//! The AVR ATtiny441 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | ATtiny441-SSU | SOIC_14 | SOIC14 | -40°C - 85°C | 1.7V - 5.5V | 16 MHz |
//! | ATtiny441-MU | QFN_20 | MLF20 | -40°C - 85°C | 1.7V - 5.5V | 16 MHz |
//! | ATtiny441-MMH | QFN_20 | VQFN20 | -40°C - 85°C | 1.7V - 5.5V | 16 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTB
//!     * PB0 (PB0)
//!     * PB1 (PB1)
//!     * PB2 (PB2)
//!     * PB3 (PB3)
//! * PORTA
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)
//!
//! ## USART modules
//!
//! * USART1
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//! * USART0
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA7 (PA7)
//!     * PB2 (PB2)
//!     * PA3 (PA3)
//!
//! ## ADC modules
//!
//! * ADC
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)
//!     * PB2 (PB2)
//!     * PB3 (PB3)
//!     * PB0 (PB0)
//!     * PB1 (PB1)
//!     * PA0 (PA0)
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// ADC Control and Status Register B.
pub const ADCSRB: *mut u8 = 0x24 as *mut u8;
/// The ADC Control and Status register.
pub const ADCSRA: *mut u8 = 0x25 as *mut u8;
/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x26 as *mut u16;
/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x26 as *mut u8;
/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x27 as *mut u8;
/// The ADC multiplexer Selection Register B.
pub const ADMUXB: *mut u8 = 0x28 as *mut u8;
/// The ADC multiplexer Selection Register A.
pub const ADMUXA: *mut u8 = 0x29 as *mut u8;
/// Analog Comparator 0 Control And Status Register A.
pub const ACSR0A: *mut u8 = 0x2A as *mut u8;
/// Analog Comparator 0 Control And Status Register B.
pub const ACSR0B: *mut u8 = 0x2B as *mut u8;
/// Analog Comparator 1 Control And Status Register A.
pub const ACSR1A: *mut u8 = 0x2C as *mut u8;
/// Analog Comparator 1 Control And Status Register B.
pub const ACSR1B: *mut u8 = 0x2D as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR1: *mut u8 = 0x2E as *mut u8;
/// Timer/Counter1 Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x2F as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR2: *mut u8 = 0x30 as *mut u8;
/// Timer/Counter2 Interrupt Mask Register.
pub const TIMSK2: *mut u8 = 0x31 as *mut u8;
/// Pin Change Enable Mask 0.
pub const PCMSK0: *mut u8 = 0x32 as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x33 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x34 as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x35 as *mut u8;
/// Port B Data register.
pub const PINB: *mut u8 = 0x36 as *mut u8;
/// Data Direction Register, Port B.
pub const DDRB: *mut u8 = 0x37 as *mut u8;
/// Input Pins, Port B.
pub const PORTB: *mut u8 = 0x38 as *mut u8;
/// Port A Input Pins.
pub const PINA: *mut u8 = 0x39 as *mut u8;
/// Data Direction Register, Port A.
pub const DDRA: *mut u8 = 0x3A as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x3B as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3C as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x3E as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x3E as *mut u16;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x3F as *mut u8;
/// Pin Change Enable Mask 1.
pub const PCMSK1: *mut u8 = 0x40 as *mut u8;
/// Watchdog Timer Control and Status Register.
pub const WDTCSR: *mut u8 = 0x41 as *mut u8;
/// Timer/Counter1 Control Register C.
pub const TCCR1C: *mut u8 = 0x42 as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x44 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x44 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x45 as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes.
pub const OCR1B: *mut u16 = 0x48 as *mut u16;
/// Timer/Counter1 Output Compare Register B  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x48 as *mut u8;
/// Timer/Counter1 Output Compare Register B  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x49 as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes.
pub const OCR1A: *mut u16 = 0x4A as *mut u16;
/// Timer/Counter1 Output Compare Register A  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x4A as *mut u8;
/// Timer/Counter1 Output Compare Register A  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x4B as *mut u8;
/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x4C as *mut u8;
/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x4C as *mut u16;
/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x4D as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x4E as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x4F as *mut u8;
/// Timer/Counter  Control Register A.
pub const TCCR0A: *mut u8 = 0x50 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x52 as *mut u8;
/// Timer/Counter Control Register B.
pub const TCCR0B: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Timer/Counter0 Output Compare Register A.
pub const OCR0A: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control and Status Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Timer/Counter0 Interrupt Flag Register.
pub const TIFR0: *mut u8 = 0x58 as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK0: *mut u8 = 0x59 as *mut u8;
/// General Interrupt Flag register.
pub const GIFR: *mut u8 = 0x5A as *mut u8;
/// General Interrupt Mask Register.
pub const GIMSK: *mut u8 = 0x5B as *mut u8;
/// Timer/Counter0 Output Compare Register B.
pub const OCR0B: *mut u8 = 0x5C as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Digital Input Disable Register 0.
pub const DIDR0: *mut u8 = 0x60 as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR1: *mut u8 = 0x61 as *mut u8;
/// Pull-up Enable Control Register.
pub const PUEB: *mut u8 = 0x62 as *mut u8;
/// Pull-up Enable Control Register.
pub const PUEA: *mut u8 = 0x63 as *mut u8;
/// Port Control Register.
pub const PORTCR: *mut u8 = 0x64 as *mut u8;
/// Remap Port Pins.
pub const REMAP: *mut u8 = 0x65 as *mut u8;
/// Timer Output Compare Pin Mux Channel Output Enable.
pub const TOCPMCOE: *mut u8 = 0x66 as *mut u8;
/// Timer Output Compare Pin Mux Selection 0.
pub const TOCPMSA0: *mut u8 = 0x67 as *mut u8;
/// Timer Output Compare Pin Mux Selection 1.
pub const TOCPMSA1: *mut u8 = 0x68 as *mut u8;
/// Port High Drive Enable Register.
pub const PHDE: *mut u8 = 0x6A as *mut u8;
/// Power Reduction Register.
pub const PRR: *mut u8 = 0x70 as *mut u8;
/// Configuration Change Protection.
pub const CCP: *mut u8 = 0x71 as *mut u8;
/// Clock Control Register.
pub const CLKCR: *mut u8 = 0x72 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x73 as *mut u8;
/// Oscillator Calibration Register 8MHz.
pub const OSCCAL0: *mut u8 = 0x74 as *mut u8;
/// Oscillator Temperature Calibration Register A.
pub const OSCTCAL0A: *mut u8 = 0x75 as *mut u8;
/// Oscillator Temperature Calibration Register B.
pub const OSCTCAL0B: *mut u8 = 0x76 as *mut u8;
/// Oscillator Calibration Register 32kHz.
pub const OSCCAL1: *mut u8 = 0x77 as *mut u8;
/// USART I/O Data Register.
pub const UDR0: *mut u8 = 0x80 as *mut u8;
/// USART Baud Rate Register  Bytes.
pub const UBRR0: *mut u16 = 0x81 as *mut u16;
/// USART Baud Rate Register  Bytes low byte.
pub const UBRR0L: *mut u8 = 0x81 as *mut u8;
/// USART Baud Rate Register  Bytes high byte.
pub const UBRR0H: *mut u8 = 0x82 as *mut u8;
/// USART Control and Status Register D.
pub const UCSR0D: *mut u8 = 0x83 as *mut u8;
/// USART Control and Status Register C.
pub const UCSR0C: *mut u8 = 0x84 as *mut u8;
/// USART Control and Status Register B.
pub const UCSR0B: *mut u8 = 0x85 as *mut u8;
/// USART Control and Status Register A.
pub const UCSR0A: *mut u8 = 0x86 as *mut u8;
/// USART I/O Data Register.
pub const UDR1: *mut u8 = 0x90 as *mut u8;
/// USART Baud Rate Register  Bytes.
pub const UBRR1: *mut u16 = 0x91 as *mut u16;
/// USART Baud Rate Register  Bytes low byte.
pub const UBRR1L: *mut u8 = 0x91 as *mut u8;
/// USART Baud Rate Register  Bytes high byte.
pub const UBRR1H: *mut u8 = 0x92 as *mut u8;
/// USART Control and Status Register D.
pub const UCSR1D: *mut u8 = 0x93 as *mut u8;
/// USART Control and Status Register C.
pub const UCSR1C: *mut u8 = 0x94 as *mut u8;
/// USART Control and Status Register B.
pub const UCSR1B: *mut u8 = 0x95 as *mut u8;
/// USART Control and Status Register A.
pub const UCSR1A: *mut u8 = 0x96 as *mut u8;
/// TWI Slave Data Register.
pub const TWSD: *mut u8 = 0xA0 as *mut u8;
/// TWI Slave Address Mask Register.
pub const TWSAM: *mut u8 = 0xA1 as *mut u8;
/// TWI Slave Address Register.
pub const TWSA: *mut u8 = 0xA2 as *mut u8;
/// TWI Slave Status Register A.
pub const TWSSRA: *mut u8 = 0xA3 as *mut u8;
/// TWI Slave Control Register B.
pub const TWSCRB: *mut u8 = 0xA4 as *mut u8;
/// TWI Slave Control Register A.
pub const TWSCRA: *mut u8 = 0xA5 as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0xB0 as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0xB1 as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0xB2 as *mut u8;
/// Timer/Counter2 Input Capture Register  Bytes low byte.
pub const ICR2L: *mut u8 = 0xC0 as *mut u8;
/// Timer/Counter2 Input Capture Register  Bytes.
pub const ICR2: *mut u16 = 0xC0 as *mut u16;
/// Timer/Counter2 Input Capture Register  Bytes high byte.
pub const ICR2H: *mut u8 = 0xC1 as *mut u8;
/// Timer/Counter2 Output Compare Register B  Bytes low byte.
pub const OCR2BL: *mut u8 = 0xC2 as *mut u8;
/// Timer/Counter2 Output Compare Register B  Bytes.
pub const OCR2B: *mut u16 = 0xC2 as *mut u16;
/// Timer/Counter2 Output Compare Register B  Bytes high byte.
pub const OCR2BH: *mut u8 = 0xC3 as *mut u8;
/// Timer/Counter2 Output Compare Register A  Bytes low byte.
pub const OCR2AL: *mut u8 = 0xC4 as *mut u8;
/// Timer/Counter2 Output Compare Register A  Bytes.
pub const OCR2A: *mut u16 = 0xC4 as *mut u16;
/// Timer/Counter2 Output Compare Register A  Bytes high byte.
pub const OCR2AH: *mut u8 = 0xC5 as *mut u8;
/// Timer/Counter2  Bytes.
pub const TCNT2: *mut u16 = 0xC6 as *mut u16;
/// Timer/Counter2  Bytes low byte.
pub const TCNT2L: *mut u8 = 0xC6 as *mut u8;
/// Timer/Counter2  Bytes high byte.
pub const TCNT2H: *mut u8 = 0xC7 as *mut u8;
/// Timer/Counter2 Control Register C.
pub const TCCR2C: *mut u8 = 0xC8 as *mut u8;
/// Timer/Counter2 Control Register B.
pub const TCCR2B: *mut u8 = 0xC9 as *mut u8;
/// Timer/Counter2 Control Register A.
pub const TCCR2A: *mut u8 = 0xCA as *mut u8;