avr_device/devices/atmega4809/spi0/
ctrla.rs

1#[doc = "Register `CTRLA` reader"]
2pub struct R(crate::R<CTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLA` writer"]
17pub struct W(crate::W<CTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENABLE` reader - Enable Module"]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - Enable Module"]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
41#[doc = "Field `PRESC` reader - Prescaler"]
42pub type PRESC_R = crate::FieldReader<u8, PRESC_A>;
43#[doc = "Prescaler\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum PRESC_A {
47    #[doc = "0: System Clock / 4"]
48    DIV4 = 0,
49    #[doc = "1: System Clock / 16"]
50    DIV16 = 1,
51    #[doc = "2: System Clock / 64"]
52    DIV64 = 2,
53    #[doc = "3: System Clock / 128"]
54    DIV128 = 3,
55}
56impl From<PRESC_A> for u8 {
57    #[inline(always)]
58    fn from(variant: PRESC_A) -> Self {
59        variant as _
60    }
61}
62impl PRESC_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> PRESC_A {
66        match self.bits {
67            0 => PRESC_A::DIV4,
68            1 => PRESC_A::DIV16,
69            2 => PRESC_A::DIV64,
70            3 => PRESC_A::DIV128,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Checks if the value of the field is `DIV4`"]
75    #[inline(always)]
76    pub fn is_div4(&self) -> bool {
77        *self == PRESC_A::DIV4
78    }
79    #[doc = "Checks if the value of the field is `DIV16`"]
80    #[inline(always)]
81    pub fn is_div16(&self) -> bool {
82        *self == PRESC_A::DIV16
83    }
84    #[doc = "Checks if the value of the field is `DIV64`"]
85    #[inline(always)]
86    pub fn is_div64(&self) -> bool {
87        *self == PRESC_A::DIV64
88    }
89    #[doc = "Checks if the value of the field is `DIV128`"]
90    #[inline(always)]
91    pub fn is_div128(&self) -> bool {
92        *self == PRESC_A::DIV128
93    }
94}
95#[doc = "Field `PRESC` writer - Prescaler"]
96pub type PRESC_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, CTRLA_SPEC, u8, PRESC_A, 2, O>;
97impl<'a, const O: u8> PRESC_W<'a, O> {
98    #[doc = "System Clock / 4"]
99    #[inline(always)]
100    pub fn div4(self) -> &'a mut W {
101        self.variant(PRESC_A::DIV4)
102    }
103    #[doc = "System Clock / 16"]
104    #[inline(always)]
105    pub fn div16(self) -> &'a mut W {
106        self.variant(PRESC_A::DIV16)
107    }
108    #[doc = "System Clock / 64"]
109    #[inline(always)]
110    pub fn div64(self) -> &'a mut W {
111        self.variant(PRESC_A::DIV64)
112    }
113    #[doc = "System Clock / 128"]
114    #[inline(always)]
115    pub fn div128(self) -> &'a mut W {
116        self.variant(PRESC_A::DIV128)
117    }
118}
119#[doc = "Field `CLK2X` reader - Enable Double Speed"]
120pub type CLK2X_R = crate::BitReader<bool>;
121#[doc = "Field `CLK2X` writer - Enable Double Speed"]
122pub type CLK2X_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
123#[doc = "Field `MASTER` reader - Master Operation Enable"]
124pub type MASTER_R = crate::BitReader<bool>;
125#[doc = "Field `MASTER` writer - Master Operation Enable"]
126pub type MASTER_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
127#[doc = "Field `DORD` reader - Data Order Setting"]
128pub type DORD_R = crate::BitReader<bool>;
129#[doc = "Field `DORD` writer - Data Order Setting"]
130pub type DORD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
131impl R {
132    #[doc = "Bit 0 - Enable Module"]
133    #[inline(always)]
134    pub fn enable(&self) -> ENABLE_R {
135        ENABLE_R::new((self.bits & 1) != 0)
136    }
137    #[doc = "Bits 1:2 - Prescaler"]
138    #[inline(always)]
139    pub fn presc(&self) -> PRESC_R {
140        PRESC_R::new((self.bits >> 1) & 3)
141    }
142    #[doc = "Bit 4 - Enable Double Speed"]
143    #[inline(always)]
144    pub fn clk2x(&self) -> CLK2X_R {
145        CLK2X_R::new(((self.bits >> 4) & 1) != 0)
146    }
147    #[doc = "Bit 5 - Master Operation Enable"]
148    #[inline(always)]
149    pub fn master(&self) -> MASTER_R {
150        MASTER_R::new(((self.bits >> 5) & 1) != 0)
151    }
152    #[doc = "Bit 6 - Data Order Setting"]
153    #[inline(always)]
154    pub fn dord(&self) -> DORD_R {
155        DORD_R::new(((self.bits >> 6) & 1) != 0)
156    }
157}
158impl W {
159    #[doc = "Bit 0 - Enable Module"]
160    #[inline(always)]
161    #[must_use]
162    pub fn enable(&mut self) -> ENABLE_W<0> {
163        ENABLE_W::new(self)
164    }
165    #[doc = "Bits 1:2 - Prescaler"]
166    #[inline(always)]
167    #[must_use]
168    pub fn presc(&mut self) -> PRESC_W<1> {
169        PRESC_W::new(self)
170    }
171    #[doc = "Bit 4 - Enable Double Speed"]
172    #[inline(always)]
173    #[must_use]
174    pub fn clk2x(&mut self) -> CLK2X_W<4> {
175        CLK2X_W::new(self)
176    }
177    #[doc = "Bit 5 - Master Operation Enable"]
178    #[inline(always)]
179    #[must_use]
180    pub fn master(&mut self) -> MASTER_W<5> {
181        MASTER_W::new(self)
182    }
183    #[doc = "Bit 6 - Data Order Setting"]
184    #[inline(always)]
185    #[must_use]
186    pub fn dord(&mut self) -> DORD_W<6> {
187        DORD_W::new(self)
188    }
189    #[doc = "Writes raw bits to the register."]
190    #[inline(always)]
191    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
192        self.0.bits(bits);
193        self
194    }
195}
196#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"]
197pub struct CTRLA_SPEC;
198impl crate::RegisterSpec for CTRLA_SPEC {
199    type Ux = u8;
200}
201#[doc = "`read()` method returns [ctrla::R](R) reader structure"]
202impl crate::Readable for CTRLA_SPEC {
203    type Reader = R;
204}
205#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"]
206impl crate::Writable for CTRLA_SPEC {
207    type Writer = W;
208    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
209    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210}
211#[doc = "`reset()` method sets CTRLA to value 0"]
212impl crate::Resettable for CTRLA_SPEC {
213    const RESET_VALUE: Self::Ux = 0;
214}
avr_device/devices/atmega4809/spi0/ctrla.rs

avr_device/devices/atmega4809/spi0/
ctrla.rs
