avr_device/devices/atmega2560/adc/
admux.rs1#[doc = "Register `ADMUX` reader"]
2pub struct R(crate::R<ADMUX_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADMUX_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADMUX_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADMUX_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ADMUX` writer"]
17pub struct W(crate::W<ADMUX_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADMUX_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADMUX_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADMUX_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `MUX` reader - Analog Channel and Gain Selection Bits"]
38pub type MUX_R = crate::FieldReader<u8, MUX_A>;
39#[doc = "Analog Channel and Gain Selection Bits\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MUX_A {
43 #[doc = "0: ADC Single Ended Input pin 0"]
44 ADC0 = 0,
45 #[doc = "1: ADC Single Ended Input pin 1"]
46 ADC1 = 1,
47 #[doc = "2: ADC Single Ended Input pin 2"]
48 ADC2 = 2,
49 #[doc = "3: ADC Single Ended Input pin 3"]
50 ADC3 = 3,
51 #[doc = "4: ADC Single Ended Input pin 4"]
52 ADC4 = 4,
53 #[doc = "5: ADC Single Ended Input pin 5"]
54 ADC5 = 5,
55 #[doc = "6: ADC Single Ended Input pin 6"]
56 ADC6 = 6,
57 #[doc = "7: ADC Single Ended Input pin 7"]
58 ADC7 = 7,
59 #[doc = "8: ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain"]
60 ADC0_ADC0_10X = 8,
61 #[doc = "9: ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain"]
62 ADC1_ADC0_10X = 9,
63 #[doc = "10: ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain"]
64 ADC0_ADC0_200X = 10,
65 #[doc = "11: ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain"]
66 ADC1_ADC0_200X = 11,
67 #[doc = "12: ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain"]
68 ADC2_ADC2_10X = 12,
69 #[doc = "13: ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain"]
70 ADC3_ADC2_10X = 13,
71 #[doc = "14: ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain"]
72 ADC2_ADC2_200X = 14,
73 #[doc = "15: ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain"]
74 ADC3_ADC2_200X = 15,
75 #[doc = "16: ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain"]
76 ADC0_ADC1_1X = 16,
77 #[doc = "17: ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain"]
78 ADC1_ADC1_1X = 17,
79 #[doc = "18: ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain"]
80 ADC2_ADC1_1X = 18,
81 #[doc = "19: ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain"]
82 ADC3_ADC1_1X = 19,
83 #[doc = "20: ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain"]
84 ADC4_ADC1_1X = 20,
85 #[doc = "21: ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain"]
86 ADC5_ADC1_1X = 21,
87 #[doc = "22: ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain"]
88 ADC6_ADC1_1X = 22,
89 #[doc = "23: ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain"]
90 ADC7_ADC1_1X = 23,
91 #[doc = "24: ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain"]
92 ADC0_ADC2_1X = 24,
93 #[doc = "25: ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain"]
94 ADC1_ADC2_1X = 25,
95 #[doc = "26: ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain"]
96 ADC2_ADC2_1X = 26,
97 #[doc = "27: ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain"]
98 ADC3_ADC2_1X = 27,
99 #[doc = "28: ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain"]
100 ADC4_ADC2_1X = 28,
101 #[doc = "29: ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain"]
102 ADC5_ADC2_1X = 29,
103 #[doc = "30: Internal Reference (VBG)"]
104 ADC_VBG = 30,
105 #[doc = "31: 0V (GND)"]
106 ADC_GND = 31,
107}
108impl From<MUX_A> for u8 {
109 #[inline(always)]
110 fn from(variant: MUX_A) -> Self {
111 variant as _
112 }
113}
114impl MUX_R {
115 #[doc = "Get enumerated values variant"]
116 #[inline(always)]
117 pub fn variant(&self) -> MUX_A {
118 match self.bits {
119 0 => MUX_A::ADC0,
120 1 => MUX_A::ADC1,
121 2 => MUX_A::ADC2,
122 3 => MUX_A::ADC3,
123 4 => MUX_A::ADC4,
124 5 => MUX_A::ADC5,
125 6 => MUX_A::ADC6,
126 7 => MUX_A::ADC7,
127 8 => MUX_A::ADC0_ADC0_10X,
128 9 => MUX_A::ADC1_ADC0_10X,
129 10 => MUX_A::ADC0_ADC0_200X,
130 11 => MUX_A::ADC1_ADC0_200X,
131 12 => MUX_A::ADC2_ADC2_10X,
132 13 => MUX_A::ADC3_ADC2_10X,
133 14 => MUX_A::ADC2_ADC2_200X,
134 15 => MUX_A::ADC3_ADC2_200X,
135 16 => MUX_A::ADC0_ADC1_1X,
136 17 => MUX_A::ADC1_ADC1_1X,
137 18 => MUX_A::ADC2_ADC1_1X,
138 19 => MUX_A::ADC3_ADC1_1X,
139 20 => MUX_A::ADC4_ADC1_1X,
140 21 => MUX_A::ADC5_ADC1_1X,
141 22 => MUX_A::ADC6_ADC1_1X,
142 23 => MUX_A::ADC7_ADC1_1X,
143 24 => MUX_A::ADC0_ADC2_1X,
144 25 => MUX_A::ADC1_ADC2_1X,
145 26 => MUX_A::ADC2_ADC2_1X,
146 27 => MUX_A::ADC3_ADC2_1X,
147 28 => MUX_A::ADC4_ADC2_1X,
148 29 => MUX_A::ADC5_ADC2_1X,
149 30 => MUX_A::ADC_VBG,
150 31 => MUX_A::ADC_GND,
151 _ => unreachable!(),
152 }
153 }
154 #[doc = "Checks if the value of the field is `ADC0`"]
155 #[inline(always)]
156 pub fn is_adc0(&self) -> bool {
157 *self == MUX_A::ADC0
158 }
159 #[doc = "Checks if the value of the field is `ADC1`"]
160 #[inline(always)]
161 pub fn is_adc1(&self) -> bool {
162 *self == MUX_A::ADC1
163 }
164 #[doc = "Checks if the value of the field is `ADC2`"]
165 #[inline(always)]
166 pub fn is_adc2(&self) -> bool {
167 *self == MUX_A::ADC2
168 }
169 #[doc = "Checks if the value of the field is `ADC3`"]
170 #[inline(always)]
171 pub fn is_adc3(&self) -> bool {
172 *self == MUX_A::ADC3
173 }
174 #[doc = "Checks if the value of the field is `ADC4`"]
175 #[inline(always)]
176 pub fn is_adc4(&self) -> bool {
177 *self == MUX_A::ADC4
178 }
179 #[doc = "Checks if the value of the field is `ADC5`"]
180 #[inline(always)]
181 pub fn is_adc5(&self) -> bool {
182 *self == MUX_A::ADC5
183 }
184 #[doc = "Checks if the value of the field is `ADC6`"]
185 #[inline(always)]
186 pub fn is_adc6(&self) -> bool {
187 *self == MUX_A::ADC6
188 }
189 #[doc = "Checks if the value of the field is `ADC7`"]
190 #[inline(always)]
191 pub fn is_adc7(&self) -> bool {
192 *self == MUX_A::ADC7
193 }
194 #[doc = "Checks if the value of the field is `ADC0_ADC0_10X`"]
195 #[inline(always)]
196 pub fn is_adc0_adc0_10x(&self) -> bool {
197 *self == MUX_A::ADC0_ADC0_10X
198 }
199 #[doc = "Checks if the value of the field is `ADC1_ADC0_10X`"]
200 #[inline(always)]
201 pub fn is_adc1_adc0_10x(&self) -> bool {
202 *self == MUX_A::ADC1_ADC0_10X
203 }
204 #[doc = "Checks if the value of the field is `ADC0_ADC0_200X`"]
205 #[inline(always)]
206 pub fn is_adc0_adc0_200x(&self) -> bool {
207 *self == MUX_A::ADC0_ADC0_200X
208 }
209 #[doc = "Checks if the value of the field is `ADC1_ADC0_200X`"]
210 #[inline(always)]
211 pub fn is_adc1_adc0_200x(&self) -> bool {
212 *self == MUX_A::ADC1_ADC0_200X
213 }
214 #[doc = "Checks if the value of the field is `ADC2_ADC2_10X`"]
215 #[inline(always)]
216 pub fn is_adc2_adc2_10x(&self) -> bool {
217 *self == MUX_A::ADC2_ADC2_10X
218 }
219 #[doc = "Checks if the value of the field is `ADC3_ADC2_10X`"]
220 #[inline(always)]
221 pub fn is_adc3_adc2_10x(&self) -> bool {
222 *self == MUX_A::ADC3_ADC2_10X
223 }
224 #[doc = "Checks if the value of the field is `ADC2_ADC2_200X`"]
225 #[inline(always)]
226 pub fn is_adc2_adc2_200x(&self) -> bool {
227 *self == MUX_A::ADC2_ADC2_200X
228 }
229 #[doc = "Checks if the value of the field is `ADC3_ADC2_200X`"]
230 #[inline(always)]
231 pub fn is_adc3_adc2_200x(&self) -> bool {
232 *self == MUX_A::ADC3_ADC2_200X
233 }
234 #[doc = "Checks if the value of the field is `ADC0_ADC1_1X`"]
235 #[inline(always)]
236 pub fn is_adc0_adc1_1x(&self) -> bool {
237 *self == MUX_A::ADC0_ADC1_1X
238 }
239 #[doc = "Checks if the value of the field is `ADC1_ADC1_1X`"]
240 #[inline(always)]
241 pub fn is_adc1_adc1_1x(&self) -> bool {
242 *self == MUX_A::ADC1_ADC1_1X
243 }
244 #[doc = "Checks if the value of the field is `ADC2_ADC1_1X`"]
245 #[inline(always)]
246 pub fn is_adc2_adc1_1x(&self) -> bool {
247 *self == MUX_A::ADC2_ADC1_1X
248 }
249 #[doc = "Checks if the value of the field is `ADC3_ADC1_1X`"]
250 #[inline(always)]
251 pub fn is_adc3_adc1_1x(&self) -> bool {
252 *self == MUX_A::ADC3_ADC1_1X
253 }
254 #[doc = "Checks if the value of the field is `ADC4_ADC1_1X`"]
255 #[inline(always)]
256 pub fn is_adc4_adc1_1x(&self) -> bool {
257 *self == MUX_A::ADC4_ADC1_1X
258 }
259 #[doc = "Checks if the value of the field is `ADC5_ADC1_1X`"]
260 #[inline(always)]
261 pub fn is_adc5_adc1_1x(&self) -> bool {
262 *self == MUX_A::ADC5_ADC1_1X
263 }
264 #[doc = "Checks if the value of the field is `ADC6_ADC1_1X`"]
265 #[inline(always)]
266 pub fn is_adc6_adc1_1x(&self) -> bool {
267 *self == MUX_A::ADC6_ADC1_1X
268 }
269 #[doc = "Checks if the value of the field is `ADC7_ADC1_1X`"]
270 #[inline(always)]
271 pub fn is_adc7_adc1_1x(&self) -> bool {
272 *self == MUX_A::ADC7_ADC1_1X
273 }
274 #[doc = "Checks if the value of the field is `ADC0_ADC2_1X`"]
275 #[inline(always)]
276 pub fn is_adc0_adc2_1x(&self) -> bool {
277 *self == MUX_A::ADC0_ADC2_1X
278 }
279 #[doc = "Checks if the value of the field is `ADC1_ADC2_1X`"]
280 #[inline(always)]
281 pub fn is_adc1_adc2_1x(&self) -> bool {
282 *self == MUX_A::ADC1_ADC2_1X
283 }
284 #[doc = "Checks if the value of the field is `ADC2_ADC2_1X`"]
285 #[inline(always)]
286 pub fn is_adc2_adc2_1x(&self) -> bool {
287 *self == MUX_A::ADC2_ADC2_1X
288 }
289 #[doc = "Checks if the value of the field is `ADC3_ADC2_1X`"]
290 #[inline(always)]
291 pub fn is_adc3_adc2_1x(&self) -> bool {
292 *self == MUX_A::ADC3_ADC2_1X
293 }
294 #[doc = "Checks if the value of the field is `ADC4_ADC2_1X`"]
295 #[inline(always)]
296 pub fn is_adc4_adc2_1x(&self) -> bool {
297 *self == MUX_A::ADC4_ADC2_1X
298 }
299 #[doc = "Checks if the value of the field is `ADC5_ADC2_1X`"]
300 #[inline(always)]
301 pub fn is_adc5_adc2_1x(&self) -> bool {
302 *self == MUX_A::ADC5_ADC2_1X
303 }
304 #[doc = "Checks if the value of the field is `ADC_VBG`"]
305 #[inline(always)]
306 pub fn is_adc_vbg(&self) -> bool {
307 *self == MUX_A::ADC_VBG
308 }
309 #[doc = "Checks if the value of the field is `ADC_GND`"]
310 #[inline(always)]
311 pub fn is_adc_gnd(&self) -> bool {
312 *self == MUX_A::ADC_GND
313 }
314}
315#[doc = "Field `MUX` writer - Analog Channel and Gain Selection Bits"]
316pub type MUX_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, ADMUX_SPEC, u8, MUX_A, 5, O>;
317impl<'a, const O: u8> MUX_W<'a, O> {
318 #[doc = "ADC Single Ended Input pin 0"]
319 #[inline(always)]
320 pub fn adc0(self) -> &'a mut W {
321 self.variant(MUX_A::ADC0)
322 }
323 #[doc = "ADC Single Ended Input pin 1"]
324 #[inline(always)]
325 pub fn adc1(self) -> &'a mut W {
326 self.variant(MUX_A::ADC1)
327 }
328 #[doc = "ADC Single Ended Input pin 2"]
329 #[inline(always)]
330 pub fn adc2(self) -> &'a mut W {
331 self.variant(MUX_A::ADC2)
332 }
333 #[doc = "ADC Single Ended Input pin 3"]
334 #[inline(always)]
335 pub fn adc3(self) -> &'a mut W {
336 self.variant(MUX_A::ADC3)
337 }
338 #[doc = "ADC Single Ended Input pin 4"]
339 #[inline(always)]
340 pub fn adc4(self) -> &'a mut W {
341 self.variant(MUX_A::ADC4)
342 }
343 #[doc = "ADC Single Ended Input pin 5"]
344 #[inline(always)]
345 pub fn adc5(self) -> &'a mut W {
346 self.variant(MUX_A::ADC5)
347 }
348 #[doc = "ADC Single Ended Input pin 6"]
349 #[inline(always)]
350 pub fn adc6(self) -> &'a mut W {
351 self.variant(MUX_A::ADC6)
352 }
353 #[doc = "ADC Single Ended Input pin 7"]
354 #[inline(always)]
355 pub fn adc7(self) -> &'a mut W {
356 self.variant(MUX_A::ADC7)
357 }
358 #[doc = "ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain"]
359 #[inline(always)]
360 pub fn adc0_adc0_10x(self) -> &'a mut W {
361 self.variant(MUX_A::ADC0_ADC0_10X)
362 }
363 #[doc = "ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain"]
364 #[inline(always)]
365 pub fn adc1_adc0_10x(self) -> &'a mut W {
366 self.variant(MUX_A::ADC1_ADC0_10X)
367 }
368 #[doc = "ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain"]
369 #[inline(always)]
370 pub fn adc0_adc0_200x(self) -> &'a mut W {
371 self.variant(MUX_A::ADC0_ADC0_200X)
372 }
373 #[doc = "ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain"]
374 #[inline(always)]
375 pub fn adc1_adc0_200x(self) -> &'a mut W {
376 self.variant(MUX_A::ADC1_ADC0_200X)
377 }
378 #[doc = "ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain"]
379 #[inline(always)]
380 pub fn adc2_adc2_10x(self) -> &'a mut W {
381 self.variant(MUX_A::ADC2_ADC2_10X)
382 }
383 #[doc = "ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain"]
384 #[inline(always)]
385 pub fn adc3_adc2_10x(self) -> &'a mut W {
386 self.variant(MUX_A::ADC3_ADC2_10X)
387 }
388 #[doc = "ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain"]
389 #[inline(always)]
390 pub fn adc2_adc2_200x(self) -> &'a mut W {
391 self.variant(MUX_A::ADC2_ADC2_200X)
392 }
393 #[doc = "ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain"]
394 #[inline(always)]
395 pub fn adc3_adc2_200x(self) -> &'a mut W {
396 self.variant(MUX_A::ADC3_ADC2_200X)
397 }
398 #[doc = "ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain"]
399 #[inline(always)]
400 pub fn adc0_adc1_1x(self) -> &'a mut W {
401 self.variant(MUX_A::ADC0_ADC1_1X)
402 }
403 #[doc = "ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain"]
404 #[inline(always)]
405 pub fn adc1_adc1_1x(self) -> &'a mut W {
406 self.variant(MUX_A::ADC1_ADC1_1X)
407 }
408 #[doc = "ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain"]
409 #[inline(always)]
410 pub fn adc2_adc1_1x(self) -> &'a mut W {
411 self.variant(MUX_A::ADC2_ADC1_1X)
412 }
413 #[doc = "ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain"]
414 #[inline(always)]
415 pub fn adc3_adc1_1x(self) -> &'a mut W {
416 self.variant(MUX_A::ADC3_ADC1_1X)
417 }
418 #[doc = "ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain"]
419 #[inline(always)]
420 pub fn adc4_adc1_1x(self) -> &'a mut W {
421 self.variant(MUX_A::ADC4_ADC1_1X)
422 }
423 #[doc = "ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain"]
424 #[inline(always)]
425 pub fn adc5_adc1_1x(self) -> &'a mut W {
426 self.variant(MUX_A::ADC5_ADC1_1X)
427 }
428 #[doc = "ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain"]
429 #[inline(always)]
430 pub fn adc6_adc1_1x(self) -> &'a mut W {
431 self.variant(MUX_A::ADC6_ADC1_1X)
432 }
433 #[doc = "ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain"]
434 #[inline(always)]
435 pub fn adc7_adc1_1x(self) -> &'a mut W {
436 self.variant(MUX_A::ADC7_ADC1_1X)
437 }
438 #[doc = "ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain"]
439 #[inline(always)]
440 pub fn adc0_adc2_1x(self) -> &'a mut W {
441 self.variant(MUX_A::ADC0_ADC2_1X)
442 }
443 #[doc = "ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain"]
444 #[inline(always)]
445 pub fn adc1_adc2_1x(self) -> &'a mut W {
446 self.variant(MUX_A::ADC1_ADC2_1X)
447 }
448 #[doc = "ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain"]
449 #[inline(always)]
450 pub fn adc2_adc2_1x(self) -> &'a mut W {
451 self.variant(MUX_A::ADC2_ADC2_1X)
452 }
453 #[doc = "ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain"]
454 #[inline(always)]
455 pub fn adc3_adc2_1x(self) -> &'a mut W {
456 self.variant(MUX_A::ADC3_ADC2_1X)
457 }
458 #[doc = "ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain"]
459 #[inline(always)]
460 pub fn adc4_adc2_1x(self) -> &'a mut W {
461 self.variant(MUX_A::ADC4_ADC2_1X)
462 }
463 #[doc = "ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain"]
464 #[inline(always)]
465 pub fn adc5_adc2_1x(self) -> &'a mut W {
466 self.variant(MUX_A::ADC5_ADC2_1X)
467 }
468 #[doc = "Internal Reference (VBG)"]
469 #[inline(always)]
470 pub fn adc_vbg(self) -> &'a mut W {
471 self.variant(MUX_A::ADC_VBG)
472 }
473 #[doc = "0V (GND)"]
474 #[inline(always)]
475 pub fn adc_gnd(self) -> &'a mut W {
476 self.variant(MUX_A::ADC_GND)
477 }
478}
479#[doc = "Field `ADLAR` reader - Left Adjust Result"]
480pub type ADLAR_R = crate::BitReader<bool>;
481#[doc = "Field `ADLAR` writer - Left Adjust Result"]
482pub type ADLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, ADMUX_SPEC, bool, O>;
483#[doc = "Field `REFS` reader - Reference Selection Bits"]
484pub type REFS_R = crate::FieldReader<u8, REFS_A>;
485#[doc = "Reference Selection Bits\n\nValue on reset: 0"]
486#[derive(Clone, Copy, Debug, PartialEq, Eq)]
487#[repr(u8)]
488pub enum REFS_A {
489 #[doc = "0: Aref Internal Vref turned off"]
490 AREF = 0,
491 #[doc = "1: AVcc with external capacitor at AREF pin"]
492 AVCC = 1,
493 #[doc = "3: Internal 1.1V Voltage Reference with external capacitor at AREF pin"]
494 INTERNAL = 3,
495}
496impl From<REFS_A> for u8 {
497 #[inline(always)]
498 fn from(variant: REFS_A) -> Self {
499 variant as _
500 }
501}
502impl REFS_R {
503 #[doc = "Get enumerated values variant"]
504 #[inline(always)]
505 pub fn variant(&self) -> Option<REFS_A> {
506 match self.bits {
507 0 => Some(REFS_A::AREF),
508 1 => Some(REFS_A::AVCC),
509 3 => Some(REFS_A::INTERNAL),
510 _ => None,
511 }
512 }
513 #[doc = "Checks if the value of the field is `AREF`"]
514 #[inline(always)]
515 pub fn is_aref(&self) -> bool {
516 *self == REFS_A::AREF
517 }
518 #[doc = "Checks if the value of the field is `AVCC`"]
519 #[inline(always)]
520 pub fn is_avcc(&self) -> bool {
521 *self == REFS_A::AVCC
522 }
523 #[doc = "Checks if the value of the field is `INTERNAL`"]
524 #[inline(always)]
525 pub fn is_internal(&self) -> bool {
526 *self == REFS_A::INTERNAL
527 }
528}
529#[doc = "Field `REFS` writer - Reference Selection Bits"]
530pub type REFS_W<'a, const O: u8> = crate::FieldWriter<'a, u8, ADMUX_SPEC, u8, REFS_A, 2, O>;
531impl<'a, const O: u8> REFS_W<'a, O> {
532 #[doc = "Aref Internal Vref turned off"]
533 #[inline(always)]
534 pub fn aref(self) -> &'a mut W {
535 self.variant(REFS_A::AREF)
536 }
537 #[doc = "AVcc with external capacitor at AREF pin"]
538 #[inline(always)]
539 pub fn avcc(self) -> &'a mut W {
540 self.variant(REFS_A::AVCC)
541 }
542 #[doc = "Internal 1.1V Voltage Reference with external capacitor at AREF pin"]
543 #[inline(always)]
544 pub fn internal(self) -> &'a mut W {
545 self.variant(REFS_A::INTERNAL)
546 }
547}
548impl R {
549 #[doc = "Bits 0:4 - Analog Channel and Gain Selection Bits"]
550 #[inline(always)]
551 pub fn mux(&self) -> MUX_R {
552 MUX_R::new(self.bits & 0x1f)
553 }
554 #[doc = "Bit 5 - Left Adjust Result"]
555 #[inline(always)]
556 pub fn adlar(&self) -> ADLAR_R {
557 ADLAR_R::new(((self.bits >> 5) & 1) != 0)
558 }
559 #[doc = "Bits 6:7 - Reference Selection Bits"]
560 #[inline(always)]
561 pub fn refs(&self) -> REFS_R {
562 REFS_R::new((self.bits >> 6) & 3)
563 }
564}
565impl W {
566 #[doc = "Bits 0:4 - Analog Channel and Gain Selection Bits"]
567 #[inline(always)]
568 #[must_use]
569 pub fn mux(&mut self) -> MUX_W<0> {
570 MUX_W::new(self)
571 }
572 #[doc = "Bit 5 - Left Adjust Result"]
573 #[inline(always)]
574 #[must_use]
575 pub fn adlar(&mut self) -> ADLAR_W<5> {
576 ADLAR_W::new(self)
577 }
578 #[doc = "Bits 6:7 - Reference Selection Bits"]
579 #[inline(always)]
580 #[must_use]
581 pub fn refs(&mut self) -> REFS_W<6> {
582 REFS_W::new(self)
583 }
584 #[doc = "Writes raw bits to the register."]
585 #[inline(always)]
586 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
587 self.0.bits(bits);
588 self
589 }
590}
591#[doc = "The ADC multiplexer Selection Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [admux](index.html) module"]
592pub struct ADMUX_SPEC;
593impl crate::RegisterSpec for ADMUX_SPEC {
594 type Ux = u8;
595}
596#[doc = "`read()` method returns [admux::R](R) reader structure"]
597impl crate::Readable for ADMUX_SPEC {
598 type Reader = R;
599}
600#[doc = "`write(|w| ..)` method takes [admux::W](W) writer structure"]
601impl crate::Writable for ADMUX_SPEC {
602 type Writer = W;
603 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
604 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
605}
606#[doc = "`reset()` method sets ADMUX to value 0"]
607impl crate::Resettable for ADMUX_SPEC {
608 const RESET_VALUE: Self::Ux = 0;
609}