avr_device/devices/atmega32u4/pll/
pllcsr.rs

1#[doc = "Register `PLLCSR` reader"]
2pub struct R(crate::R<PLLCSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLLCSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLLCSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLLCSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLLCSR` writer"]
17pub struct W(crate::W<PLLCSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLLCSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLLCSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLLCSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PLOCK` reader - PLL Lock Status Bit"]
38pub type PLOCK_R = crate::BitReader<bool>;
39#[doc = "Field `PLLE` reader - PLL Enable Bit"]
40pub type PLLE_R = crate::BitReader<bool>;
41#[doc = "Field `PLLE` writer - PLL Enable Bit"]
42pub type PLLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLCSR_SPEC, bool, O>;
43#[doc = "Field `PINDIV` reader - PLL prescaler Bit 2"]
44pub type PINDIV_R = crate::BitReader<bool>;
45#[doc = "Field `PINDIV` writer - PLL prescaler Bit 2"]
46pub type PINDIV_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLCSR_SPEC, bool, O>;
47impl R {
48    #[doc = "Bit 0 - PLL Lock Status Bit"]
49    #[inline(always)]
50    pub fn plock(&self) -> PLOCK_R {
51        PLOCK_R::new((self.bits & 1) != 0)
52    }
53    #[doc = "Bit 1 - PLL Enable Bit"]
54    #[inline(always)]
55    pub fn plle(&self) -> PLLE_R {
56        PLLE_R::new(((self.bits >> 1) & 1) != 0)
57    }
58    #[doc = "Bit 4 - PLL prescaler Bit 2"]
59    #[inline(always)]
60    pub fn pindiv(&self) -> PINDIV_R {
61        PINDIV_R::new(((self.bits >> 4) & 1) != 0)
62    }
63}
64impl W {
65    #[doc = "Bit 1 - PLL Enable Bit"]
66    #[inline(always)]
67    #[must_use]
68    pub fn plle(&mut self) -> PLLE_W<1> {
69        PLLE_W::new(self)
70    }
71    #[doc = "Bit 4 - PLL prescaler Bit 2"]
72    #[inline(always)]
73    #[must_use]
74    pub fn pindiv(&mut self) -> PINDIV_W<4> {
75        PINDIV_W::new(self)
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "PLL Status and Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pllcsr](index.html) module"]
85pub struct PLLCSR_SPEC;
86impl crate::RegisterSpec for PLLCSR_SPEC {
87    type Ux = u8;
88}
89#[doc = "`read()` method returns [pllcsr::R](R) reader structure"]
90impl crate::Readable for PLLCSR_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [pllcsr::W](W) writer structure"]
94impl crate::Writable for PLLCSR_SPEC {
95    type Writer = W;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
98}
99#[doc = "`reset()` method sets PLLCSR to value 0"]
100impl crate::Resettable for PLLCSR_SPEC {
101    const RESET_VALUE: Self::Ux = 0;
102}
avr_device/devices/atmega32u4/pll/pllcsr.rs

avr_device/devices/atmega32u4/pll/
pllcsr.rs
