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#[doc = "Reader of register UCSR2C"] pub type R = crate::R<u8, super::UCSR2C>; #[doc = "Writer for register UCSR2C"] pub type W = crate::W<u8, super::UCSR2C>; #[doc = "Register UCSR2C `reset()`'s with value 0"] impl crate::ResetValue for super::UCSR2C { #[inline(always)] fn reset_value() -> Self::Ux { 0 } } #[doc = "Clock Polarity\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum UCPOL2_A { #[doc = "0: Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] RISING_EDGE = 0, #[doc = "1: Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] FALLING_EDGE = 1, } impl From<UCPOL2_A> for bool { #[inline(always)] fn from(variant: UCPOL2_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `UCPOL2`"] pub type UCPOL2_R = crate::R<bool, UCPOL2_A>; impl UCPOL2_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> UCPOL2_A { match self.bits { false => UCPOL2_A::RISING_EDGE, true => UCPOL2_A::FALLING_EDGE, } } #[doc = "Checks if the value of the field is `RISING_EDGE`"] #[inline(always)] pub fn is_rising_edge(&self) -> bool { *self == UCPOL2_A::RISING_EDGE } #[doc = "Checks if the value of the field is `FALLING_EDGE`"] #[inline(always)] pub fn is_falling_edge(&self) -> bool { *self == UCPOL2_A::FALLING_EDGE } } #[doc = "Write proxy for field `UCPOL2`"] pub struct UCPOL2_W<'a> { w: &'a mut W, } impl<'a> UCPOL2_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: UCPOL2_A) -> &'a mut W { self.bit(variant.into()) } #[doc = "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"] #[inline(always)] pub fn rising_edge(self) -> &'a mut W { self.variant(UCPOL2_A::RISING_EDGE) } #[doc = "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"] #[inline(always)] pub fn falling_edge(self) -> &'a mut W { self.variant(UCPOL2_A::FALLING_EDGE) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01); self.w } } #[doc = "Character Size\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum UCSZ2_A { #[doc = "0: Character Size: 5 bit"] CHR5 = 0, #[doc = "1: Character Size: 6 bit"] CHR6 = 1, #[doc = "2: Character Size: 7 bit"] CHR7 = 2, #[doc = "3: Character Size: 8 bit"] CHR8 = 3, } impl From<UCSZ2_A> for u8 { #[inline(always)] fn from(variant: UCSZ2_A) -> Self { variant as _ } } #[doc = "Reader of field `UCSZ2`"] pub type UCSZ2_R = crate::R<u8, UCSZ2_A>; impl UCSZ2_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> UCSZ2_A { match self.bits { 0 => UCSZ2_A::CHR5, 1 => UCSZ2_A::CHR6, 2 => UCSZ2_A::CHR7, 3 => UCSZ2_A::CHR8, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `CHR5`"] #[inline(always)] pub fn is_chr5(&self) -> bool { *self == UCSZ2_A::CHR5 } #[doc = "Checks if the value of the field is `CHR6`"] #[inline(always)] pub fn is_chr6(&self) -> bool { *self == UCSZ2_A::CHR6 } #[doc = "Checks if the value of the field is `CHR7`"] #[inline(always)] pub fn is_chr7(&self) -> bool { *self == UCSZ2_A::CHR7 } #[doc = "Checks if the value of the field is `CHR8`"] #[inline(always)] pub fn is_chr8(&self) -> bool { *self == UCSZ2_A::CHR8 } } #[doc = "Write proxy for field `UCSZ2`"] pub struct UCSZ2_W<'a> { w: &'a mut W, } impl<'a> UCSZ2_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: UCSZ2_A) -> &'a mut W { self.bits(variant.into()) } #[doc = "Character Size: 5 bit"] #[inline(always)] pub fn chr5(self) -> &'a mut W { self.variant(UCSZ2_A::CHR5) } #[doc = "Character Size: 6 bit"] #[inline(always)] pub fn chr6(self) -> &'a mut W { self.variant(UCSZ2_A::CHR6) } #[doc = "Character Size: 7 bit"] #[inline(always)] pub fn chr7(self) -> &'a mut W { self.variant(UCSZ2_A::CHR7) } #[doc = "Character Size: 8 bit"] #[inline(always)] pub fn chr8(self) -> &'a mut W { self.variant(UCSZ2_A::CHR8) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 1)) | (((value as u8) & 0x03) << 1); self.w } } #[doc = "Stop Bit Select\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum USBS2_A { #[doc = "0: 1-bit"] STOP1 = 0, #[doc = "1: 2-bit"] STOP2 = 1, } impl From<USBS2_A> for bool { #[inline(always)] fn from(variant: USBS2_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `USBS2`"] pub type USBS2_R = crate::R<bool, USBS2_A>; impl USBS2_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> USBS2_A { match self.bits { false => USBS2_A::STOP1, true => USBS2_A::STOP2, } } #[doc = "Checks if the value of the field is `STOP1`"] #[inline(always)] pub fn is_stop1(&self) -> bool { *self == USBS2_A::STOP1 } #[doc = "Checks if the value of the field is `STOP2`"] #[inline(always)] pub fn is_stop2(&self) -> bool { *self == USBS2_A::STOP2 } } #[doc = "Write proxy for field `USBS2`"] pub struct USBS2_W<'a> { w: &'a mut W, } impl<'a> USBS2_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: USBS2_A) -> &'a mut W { self.bit(variant.into()) } #[doc = "1-bit"] #[inline(always)] pub fn stop1(self) -> &'a mut W { self.variant(USBS2_A::STOP1) } #[doc = "2-bit"] #[inline(always)] pub fn stop2(self) -> &'a mut W { self.variant(USBS2_A::STOP2) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u8) & 0x01) << 3); self.w } } #[doc = "Parity Mode Bits\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum UPM2_A { #[doc = "0: Disabled"] DISABLED = 0, #[doc = "2: Enabled, Even Parity"] PARITY_EVEN = 2, #[doc = "3: Enabled, Odd Parity"] PARITY_ODD = 3, } impl From<UPM2_A> for u8 { #[inline(always)] fn from(variant: UPM2_A) -> Self { variant as _ } } #[doc = "Reader of field `UPM2`"] pub type UPM2_R = crate::R<u8, UPM2_A>; impl UPM2_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, UPM2_A> { use crate::Variant::*; match self.bits { 0 => Val(UPM2_A::DISABLED), 2 => Val(UPM2_A::PARITY_EVEN), 3 => Val(UPM2_A::PARITY_ODD), i => Res(i), } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == UPM2_A::DISABLED } #[doc = "Checks if the value of the field is `PARITY_EVEN`"] #[inline(always)] pub fn is_parity_even(&self) -> bool { *self == UPM2_A::PARITY_EVEN } #[doc = "Checks if the value of the field is `PARITY_ODD`"] #[inline(always)] pub fn is_parity_odd(&self) -> bool { *self == UPM2_A::PARITY_ODD } } #[doc = "Write proxy for field `UPM2`"] pub struct UPM2_W<'a> { w: &'a mut W, } impl<'a> UPM2_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: UPM2_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Disabled"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(UPM2_A::DISABLED) } #[doc = "Enabled, Even Parity"] #[inline(always)] pub fn parity_even(self) -> &'a mut W { self.variant(UPM2_A::PARITY_EVEN) } #[doc = "Enabled, Odd Parity"] #[inline(always)] pub fn parity_odd(self) -> &'a mut W { self.variant(UPM2_A::PARITY_ODD) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u8) & 0x03) << 4); self.w } } #[doc = "USART Mode Select\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum UMSEL2_A { #[doc = "0: Asynchronous USART"] USART_ASYNC = 0, #[doc = "1: Synchronous USART"] USART_SYNC = 1, #[doc = "3: Master SPI (MSPIM)"] SPI_MASTER = 3, } impl From<UMSEL2_A> for u8 { #[inline(always)] fn from(variant: UMSEL2_A) -> Self { variant as _ } } #[doc = "Reader of field `UMSEL2`"] pub type UMSEL2_R = crate::R<u8, UMSEL2_A>; impl UMSEL2_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, UMSEL2_A> { use crate::Variant::*; match self.bits { 0 => Val(UMSEL2_A::USART_ASYNC), 1 => Val(UMSEL2_A::USART_SYNC), 3 => Val(UMSEL2_A::SPI_MASTER), i => Res(i), } } #[doc = "Checks if the value of the field is `USART_ASYNC`"] #[inline(always)] pub fn is_usart_async(&self) -> bool { *self == UMSEL2_A::USART_ASYNC } #[doc = "Checks if the value of the field is `USART_SYNC`"] #[inline(always)] pub fn is_usart_sync(&self) -> bool { *self == UMSEL2_A::USART_SYNC } #[doc = "Checks if the value of the field is `SPI_MASTER`"] #[inline(always)] pub fn is_spi_master(&self) -> bool { *self == UMSEL2_A::SPI_MASTER } } #[doc = "Write proxy for field `UMSEL2`"] pub struct UMSEL2_W<'a> { w: &'a mut W, } impl<'a> UMSEL2_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: UMSEL2_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Asynchronous USART"] #[inline(always)] pub fn usart_async(self) -> &'a mut W { self.variant(UMSEL2_A::USART_ASYNC) } #[doc = "Synchronous USART"] #[inline(always)] pub fn usart_sync(self) -> &'a mut W { self.variant(UMSEL2_A::USART_SYNC) } #[doc = "Master SPI (MSPIM)"] #[inline(always)] pub fn spi_master(self) -> &'a mut W { self.variant(UMSEL2_A::SPI_MASTER) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u8) & 0x03) << 6); self.w } } impl R { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] pub fn ucpol2(&self) -> UCPOL2_R { UCPOL2_R::new((self.bits & 0x01) != 0) } #[doc = "Bits 1:2 - Character Size"] #[inline(always)] pub fn ucsz2(&self) -> UCSZ2_R { UCSZ2_R::new(((self.bits >> 1) & 0x03) as u8) } #[doc = "Bit 3 - Stop Bit Select"] #[inline(always)] pub fn usbs2(&self) -> USBS2_R { USBS2_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bits 4:5 - Parity Mode Bits"] #[inline(always)] pub fn upm2(&self) -> UPM2_R { UPM2_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bits 6:7 - USART Mode Select"] #[inline(always)] pub fn umsel2(&self) -> UMSEL2_R { UMSEL2_R::new(((self.bits >> 6) & 0x03) as u8) } } impl W { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] pub fn ucpol2(&mut self) -> UCPOL2_W { UCPOL2_W { w: self } } #[doc = "Bits 1:2 - Character Size"] #[inline(always)] pub fn ucsz2(&mut self) -> UCSZ2_W { UCSZ2_W { w: self } } #[doc = "Bit 3 - Stop Bit Select"] #[inline(always)] pub fn usbs2(&mut self) -> USBS2_W { USBS2_W { w: self } } #[doc = "Bits 4:5 - Parity Mode Bits"] #[inline(always)] pub fn upm2(&mut self) -> UPM2_W { UPM2_W { w: self } } #[doc = "Bits 6:7 - USART Mode Select"] #[inline(always)] pub fn umsel2(&mut self) -> UMSEL2_W { UMSEL2_W { w: self } } }