1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
use autd3_core::{link::Link, CPUControlFlags, RxDatagram, TxDatagram};
use autd3_firmware_emulator::Emulator;
pub struct Debug {
emulator: Emulator,
}
impl Debug {
pub fn new(n: usize) -> Self {
Self {
emulator: Emulator::new(n),
}
}
}
impl Link for Debug {
fn open(&mut self) -> anyhow::Result<()> {
log::info!("Open Debug link");
self.emulator.init();
log::info!("Initialize emulator");
Ok(())
}
fn close(&mut self) -> anyhow::Result<()> {
log::info!("Close Debug link");
Ok(())
}
fn send(&mut self, tx: &TxDatagram) -> anyhow::Result<bool> {
log::info!("Send data");
log::info!("\tCPU Flag: {:?}", tx.header().cpu_flag);
log::info!("\tFPGA Flag: {:?}", tx.header().fpga_flag);
self.emulator.send(tx);
self.emulator.cpus().iter().for_each(|cpu| {
log::info!("Status: {}", cpu.id());
let fpga = cpu.fpga();
if fpga.is_stm_mode() {
if fpga.is_stm_gain_mode() {
if fpga.is_legacy_mode() {
log::info!("\tGain STM Legacy mode");
} else {
log::info!("\tGain STM mode");
}
} else {
log::info!("\tPoint STM mode");
}
if tx.header().cpu_flag.contains(CPUControlFlags::STM_BEGIN) {
log::info!("\t\tSTM BEGIN");
}
if tx.header().cpu_flag.contains(CPUControlFlags::STM_END) {
log::info!(
"\t\tSTM END (cycle = {}, frequency_division = {})",
fpga.stm_cycle(),
fpga.stm_frequency_division()
);
fpga.drives().iter().enumerate().for_each(|(i, d)| {
let (duty, phase) = d;
log::debug!("\tSTM[{}]:", i);
log::debug!(
"{}",
duty.iter()
.zip(phase.iter())
.enumerate()
.map(|(i, (d, p))| {
format!("\n\t\t{}: duty = {}, phase = {}", i, d.duty, p.phase)
})
.collect::<Vec<_>>()
.join("")
);
})
}
} else if fpga.is_legacy_mode() {
log::info!("\tNormal Legacy mode");
} else {
log::info!("\tNormal mode");
}
log::info!(
"\tSilencer step = {}, cycle={}",
fpga.silencer_step(),
fpga.silencer_cycle()
);
let (m, freq_div_m) = fpga.modulation();
log::info!(
"\tModulation size = {}, frequency_division = {}",
m.len(),
freq_div_m
);
if m.iter().take(fpga.modulation_cycle()).any(|&d| d != 0) {
log::debug!("\t\t modulation = {:?}", m);
if !fpga.is_stm_mode() {
let (duty, phase) = fpga.drives()[0];
log::debug!(
"{}",
duty.iter()
.zip(phase.iter())
.enumerate()
.map(|(i, (d, p))| {
format!("\n\t{}: duty = {}, phase = {}", i, d.duty, p.phase)
})
.collect::<Vec<_>>()
.join("")
);
}
} else {
log::info!("\tWithout output");
}
});
Ok(true)
}
fn receive(&mut self, rx: &mut RxDatagram) -> anyhow::Result<bool> {
log::info!("Receive data");
self.emulator.read(rx);
Ok(true)
}
fn cycle_ticks(&self) -> u16 {
0
}
fn is_open(&self) -> bool {
true
}
}
