autd3_firmware_emulator/fpga/
params.rs

1pub const VERSION_NUM_MAJOR: u8 = 0xA4;
2pub const VERSION_NUM_MINOR: u8 = 0x00;
3
4pub const BRAM_SELECT_CONTROLLER: u8 = 0x0;
5pub const BRAM_SELECT_MOD: u8 = 0x1;
6pub const BRAM_SELECT_PWE_TABLE: u8 = 0x2;
7pub const BRAM_SELECT_STM: u8 = 0x3;
8
9pub const BRAM_CNT_SEL_MAIN: usize = 0x00;
10pub const BRAM_CNT_SEL_PHASE_CORR: usize = 0x01;
11
12pub const TRANSITION_MODE_SYNC_IDX: u8 = 0x00;
13pub const TRANSITION_MODE_SYS_TIME: u8 = 0x01;
14pub const TRANSITION_MODE_GPIO: u8 = 0x02;
15pub const TRANSITION_MODE_EXT: u8 = 0xF0;
16pub const TRANSITION_MODE_IMMEDIATE: u8 = 0xFF;
17
18// pub const STM_MODE_FOCUS: u16 = 0x0;
19pub const STM_MODE_GAIN: u16 = 0x1;
20
21pub const SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE: u16 = 0;
22pub const SILENCER_FLAG_FIXED_UPDATE_RATE_MODE: u16 = 1 << SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE;
23
24pub const ADDR_CTL_FLAG: usize = 0x00;
25pub const ADDR_FPGA_STATE: usize = 0x01;
26pub const ADDR_VERSION_NUM_MAJOR: usize = 0x02;
27pub const ADDR_VERSION_NUM_MINOR: usize = 0x03;
28pub const ADDR_ECAT_SYNC_TIME_0: usize = 0x10;
29pub const ADDR_ECAT_SYNC_TIME_1: usize = 0x11;
30pub const ADDR_ECAT_SYNC_TIME_2: usize = 0x12;
31pub const ADDR_ECAT_SYNC_TIME_3: usize = 0x13;
32pub const ADDR_MOD_MEM_WR_SEGMENT: usize = 0x20;
33pub const ADDR_MOD_MEM_WR_PAGE: usize = 0x21;
34pub const ADDR_MOD_REQ_RD_SEGMENT: usize = 0x22;
35pub const ADDR_MOD_CYCLE0: usize = 0x23;
36pub const ADDR_MOD_CYCLE1: usize = 0x24;
37pub const ADDR_MOD_FREQ_DIV0: usize = 0x25;
38pub const ADDR_MOD_FREQ_DIV1: usize = 0x26;
39pub const ADDR_MOD_REP0: usize = 0x27;
40pub const ADDR_MOD_REP1: usize = 0x28;
41pub const ADDR_MOD_TRANSITION_MODE: usize = 0x29;
42pub const ADDR_MOD_TRANSITION_VALUE_0: usize = 0x2A;
43pub const ADDR_MOD_TRANSITION_VALUE_1: usize = 0x2B;
44pub const ADDR_MOD_TRANSITION_VALUE_2: usize = 0x2C;
45pub const ADDR_MOD_TRANSITION_VALUE_3: usize = 0x2D;
46pub const ADDR_SILENCER_FLAG: usize = 0x40;
47pub const ADDR_SILENCER_UPDATE_RATE_INTENSITY: usize = 0x41;
48pub const ADDR_SILENCER_UPDATE_RATE_PHASE: usize = 0x42;
49pub const ADDR_SILENCER_COMPLETION_STEPS_INTENSITY: usize = 0x43;
50pub const ADDR_SILENCER_COMPLETION_STEPS_PHASE: usize = 0x44;
51pub const ADDR_STM_MEM_WR_SEGMENT: usize = 0x50;
52pub const ADDR_STM_MEM_WR_PAGE: usize = 0x51;
53pub const ADDR_STM_REQ_RD_SEGMENT: usize = 0x52;
54pub const ADDR_STM_CYCLE0: usize = 0x53;
55pub const ADDR_STM_CYCLE1: usize = 0x54;
56pub const ADDR_STM_FREQ_DIV0: usize = 0x55;
57pub const ADDR_STM_FREQ_DIV1: usize = 0x56;
58pub const ADDR_STM_REP0: usize = 0x57;
59pub const ADDR_STM_REP1: usize = 0x58;
60pub const ADDR_STM_MODE0: usize = 0x59;
61pub const ADDR_STM_MODE1: usize = 0x5A;
62pub const ADDR_STM_SOUND_SPEED0: usize = 0x5B;
63pub const ADDR_STM_SOUND_SPEED1: usize = 0x5C;
64pub const ADDR_STM_NUM_FOCI0: usize = 0x5D;
65pub const ADDR_STM_NUM_FOCI1: usize = 0x5E;
66pub const ADDR_STM_TRANSITION_MODE: usize = 0x5F;
67pub const ADDR_STM_TRANSITION_VALUE_0: usize = 0x60;
68pub const ADDR_STM_TRANSITION_VALUE_1: usize = 0x61;
69pub const ADDR_STM_TRANSITION_VALUE_2: usize = 0x62;
70pub const ADDR_STM_TRANSITION_VALUE_3: usize = 0x63;
71pub const ADDR_DEBUG_VALUE0_0: usize = 0xF0;
72pub const ADDR_DEBUG_VALUE0_1: usize = 0xF1;
73pub const ADDR_DEBUG_VALUE0_2: usize = 0xF2;
74pub const ADDR_DEBUG_VALUE0_3: usize = 0xF3;
75pub const ADDR_DEBUG_VALUE1_0: usize = 0xF4;
76pub const ADDR_DEBUG_VALUE1_1: usize = 0xF5;
77pub const ADDR_DEBUG_VALUE1_2: usize = 0xF6;
78pub const ADDR_DEBUG_VALUE1_3: usize = 0xF7;
79pub const ADDR_DEBUG_VALUE2_0: usize = 0xF8;
80pub const ADDR_DEBUG_VALUE2_1: usize = 0xF9;
81pub const ADDR_DEBUG_VALUE2_2: usize = 0xFA;
82pub const ADDR_DEBUG_VALUE2_3: usize = 0xFB;
83pub const ADDR_DEBUG_VALUE3_0: usize = 0xFC;
84pub const ADDR_DEBUG_VALUE3_1: usize = 0xFD;
85pub const ADDR_DEBUG_VALUE3_2: usize = 0xFE;
86pub const ADDR_DEBUG_VALUE3_3: usize = 0xFF;
87
88pub const CTL_FLAG_MOD_SET_BIT: u16 = 0;
89pub const CTL_FLAG_STM_SET_BIT: u16 = 1;
90// pub const CTL_FLAG_SILENCER_SET_BIT: u8 = 2;
91// pub const CTL_FLAG_PULSE_WIDTH_ENCODER_SET_BIT: u8 = 3;
92// pub const CTL_FLAG_DEBUG_SET_BIT: u8 = 4;
93// pub const CTL_FLAG_SYNC_SET_BIT: u8 = 5;
94
95pub const CTL_FLAG_BIT_GPIO_IN_0: u8 = 8;
96pub const CTL_FLAG_BIT_GPIO_IN_1: u8 = 9;
97pub const CTL_FLAG_BIT_GPIO_IN_2: u8 = 10;
98pub const CTL_FLAG_BIT_GPIO_IN_3: u8 = 11;
99pub const CTL_FLAG_FORCE_FAN_BIT: u8 = 13;
100
101pub const ENABLED_EMULATOR_BIT: u8 = 0x80;
102pub const ENABLED_FEATURES_BITS: u8 = ENABLED_EMULATOR_BIT;
103
104pub const GPIO_O_TYPE_NONE: u8 = 0x00;
105pub const GPIO_O_TYPE_BASE_SIG: u8 = 0x01;
106pub const GPIO_O_TYPE_THERMO: u8 = 0x02;
107pub const GPIO_O_TYPE_FORCE_FAN: u8 = 0x03;
108pub const GPIO_O_TYPE_SYNC: u8 = 0x10;
109pub const GPIO_O_TYPE_MOD_SEGMENT: u8 = 0x20;
110pub const GPIO_O_TYPE_MOD_IDX: u8 = 0x21;
111pub const GPIO_O_TYPE_STM_SEGMENT: u8 = 0x50;
112pub const GPIO_O_TYPE_STM_IDX: u8 = 0x51;
113pub const GPIO_O_TYPE_IS_STM_MODE: u8 = 0x52;
114pub const GPIO_O_TYPE_SYS_TIME_EQ: u8 = 0x60;
115pub const GPIO_O_TYPE_SYNC_DIFF: u8 = 0x70;
116pub const GPIO_O_TYPE_PWM_OUT: u8 = 0xE0;
117pub const GPIO_O_TYPE_DIRECT: u8 = 0xF0;
autd3_firmware_emulator/fpga/params.rs

autd3_firmware_emulator/fpga/
params.rs
