autd3_firmware_emulator/fpga/
params.rs

1pub const VERSION_NUM_MAJOR: u8 = 0xA2;
2pub const VERSION_NUM_MINOR: u8 = 0x01;
3
4pub const BRAM_SELECT_CONTROLLER: u8 = 0x0;
5pub const BRAM_SELECT_MOD: u8 = 0x1;
6pub const BRAM_SELECT_PWE_TABLE: u8 = 0x2;
7pub const BRAM_SELECT_STM: u8 = 0x3;
8
9pub const BRAM_CNT_SEL_MAIN: usize = 0x00;
10pub const BRAM_CNT_SEL_PHASE_CORR: usize = 0x01;
11pub const BRAM_CNT_SEL_CLOCK: usize = 0x02;
12
13pub const TRANSITION_MODE_SYNC_IDX: u8 = 0x00;
14pub const TRANSITION_MODE_SYS_TIME: u8 = 0x01;
15pub const TRANSITION_MODE_GPIO: u8 = 0x02;
16pub const TRANSITION_MODE_EXT: u8 = 0xF0;
17pub const TRANSITION_MODE_IMMEDIATE: u8 = 0xFF;
18
19// pub const STM_MODE_FOCUS: u16 = 0x0;
20pub const STM_MODE_GAIN: u16 = 0x1;
21
22pub const SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE: u16 = 0;
23pub const SILENCER_FLAG_FIXED_UPDATE_RATE_MODE: u16 = 1 << SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE;
24pub const SILENCER_FLAG_BIT_PULSE_WIDTH: u16 = 1;
25pub const SILENCER_FLAG_PULSE_WIDTH: u16 = 1 << SILENCER_FLAG_BIT_PULSE_WIDTH;
26
27pub const ADDR_CTL_FLAG: usize = 0x00;
28pub const ADDR_FPGA_STATE: usize = 0x01;
29pub const ADDR_VERSION_NUM_MAJOR: usize = 0x02;
30pub const ADDR_VERSION_NUM_MINOR: usize = 0x03;
31pub const ADDR_ECAT_SYNC_TIME_0: usize = 0x10;
32pub const ADDR_ECAT_SYNC_TIME_1: usize = 0x11;
33pub const ADDR_ECAT_SYNC_TIME_2: usize = 0x12;
34pub const ADDR_ECAT_SYNC_TIME_3: usize = 0x13;
35pub const ADDR_MOD_MEM_WR_SEGMENT: usize = 0x20;
36pub const ADDR_MOD_REQ_RD_SEGMENT: usize = 0x21;
37pub const ADDR_MOD_CYCLE0: usize = 0x22;
38pub const ADDR_MOD_FREQ_DIV0: usize = 0x23;
39pub const ADDR_MOD_REP0: usize = 0x24;
40pub const ADDR_MOD_CYCLE1: usize = 0x25;
41pub const ADDR_MOD_FREQ_DIV1: usize = 0x26;
42pub const ADDR_MOD_REP1: usize = 0x27;
43pub const ADDR_MOD_TRANSITION_MODE: usize = 0x28;
44pub const ADDR_MOD_TRANSITION_VALUE_0: usize = 0x29;
45pub const ADDR_MOD_TRANSITION_VALUE_1: usize = 0x2A;
46pub const ADDR_MOD_TRANSITION_VALUE_2: usize = 0x2B;
47pub const ADDR_MOD_TRANSITION_VALUE_3: usize = 0x2C;
48pub const ADDR_SILENCER_FLAG: usize = 0x40;
49pub const ADDR_SILENCER_UPDATE_RATE_INTENSITY: usize = 0x41;
50pub const ADDR_SILENCER_UPDATE_RATE_PHASE: usize = 0x42;
51pub const ADDR_SILENCER_COMPLETION_STEPS_INTENSITY: usize = 0x43;
52pub const ADDR_SILENCER_COMPLETION_STEPS_PHASE: usize = 0x44;
53pub const ADDR_STM_MEM_WR_SEGMENT: usize = 0x50;
54pub const ADDR_STM_MEM_WR_PAGE: usize = 0x51;
55pub const ADDR_STM_REQ_RD_SEGMENT: usize = 0x52;
56pub const ADDR_STM_CYCLE0: usize = 0x53;
57pub const ADDR_STM_FREQ_DIV0: usize = 0x54;
58pub const ADDR_STM_REP0: usize = 0x55;
59pub const ADDR_STM_MODE0: usize = 0x56;
60pub const ADDR_STM_SOUND_SPEED0: usize = 0x57;
61pub const ADDR_STM_NUM_FOCI0: usize = 0x58;
62pub const ADDR_STM_CYCLE1: usize = 0x59;
63pub const ADDR_STM_FREQ_DIV1: usize = 0x5A;
64pub const ADDR_STM_REP1: usize = 0x5B;
65pub const ADDR_STM_MODE1: usize = 0x5C;
66pub const ADDR_STM_SOUND_SPEED1: usize = 0x5D;
67pub const ADDR_STM_NUM_FOCI1: usize = 0x5E;
68pub const ADDR_STM_TRANSITION_MODE: usize = 0x5F;
69pub const ADDR_STM_TRANSITION_VALUE_0: usize = 0x60;
70pub const ADDR_STM_TRANSITION_VALUE_1: usize = 0x61;
71pub const ADDR_STM_TRANSITION_VALUE_2: usize = 0x62;
72pub const ADDR_STM_TRANSITION_VALUE_3: usize = 0x63;
73pub const ADDR_DEBUG_VALUE0_0: usize = 0xF0;
74pub const ADDR_DEBUG_VALUE0_1: usize = 0xF1;
75pub const ADDR_DEBUG_VALUE0_2: usize = 0xF2;
76pub const ADDR_DEBUG_VALUE0_3: usize = 0xF3;
77pub const ADDR_DEBUG_VALUE1_0: usize = 0xF4;
78pub const ADDR_DEBUG_VALUE1_1: usize = 0xF5;
79pub const ADDR_DEBUG_VALUE1_2: usize = 0xF6;
80pub const ADDR_DEBUG_VALUE1_3: usize = 0xF7;
81pub const ADDR_DEBUG_VALUE2_0: usize = 0xF8;
82pub const ADDR_DEBUG_VALUE2_1: usize = 0xF9;
83pub const ADDR_DEBUG_VALUE2_2: usize = 0xFA;
84pub const ADDR_DEBUG_VALUE2_3: usize = 0xFB;
85pub const ADDR_DEBUG_VALUE3_0: usize = 0xFC;
86pub const ADDR_DEBUG_VALUE3_1: usize = 0xFD;
87pub const ADDR_DEBUG_VALUE3_2: usize = 0xFE;
88pub const ADDR_DEBUG_VALUE3_3: usize = 0xFF;
89
90pub const CTL_FLAG_MOD_SET_BIT: u16 = 0;
91pub const CTL_FLAG_STM_SET_BIT: u16 = 1;
92// pub const CTL_FLAG_SILENCER_SET_BIT: u8 = 2;
93// pub const CTL_FLAG_PULSE_WIDTH_ENCODER_SET_BIT: u8 = 3;
94// pub const CTL_FLAG_DEBUG_SET_BIT: u8 = 4;
95// pub const CTL_FLAG_SYNC_SET_BIT: u8 = 5;
96
97pub const CTL_FLAG_BIT_GPIO_IN_0: u8 = 8;
98pub const CTL_FLAG_BIT_GPIO_IN_1: u8 = 9;
99pub const CTL_FLAG_BIT_GPIO_IN_2: u8 = 10;
100pub const CTL_FLAG_BIT_GPIO_IN_3: u8 = 11;
101pub const CTL_FLAG_FORCE_FAN_BIT: u8 = 13;
102
103pub const ENABLED_EMULATOR_BIT: u8 = 0x80;
104pub const ENABLED_FEATURES_BITS: u8 = ENABLED_EMULATOR_BIT;
105
106pub const DBG_NONE: u8 = 0x00;
107pub const DBG_BASE_SIG: u8 = 0x01;
108pub const DBG_THERMO: u8 = 0x02;
109pub const DBG_FORCE_FAN: u8 = 0x03;
110pub const DBG_SYNC: u8 = 0x10;
111pub const DBG_MOD_SEGMENT: u8 = 0x20;
112pub const DBG_MOD_IDX: u8 = 0x21;
113pub const DBG_STM_SEGMENT: u8 = 0x50;
114pub const DBG_STM_IDX: u8 = 0x51;
115pub const DBG_IS_STM_MODE: u8 = 0x52;
116pub const DBG_SYS_TIME_EQ: u8 = 0x60;
117pub const DBG_PWM_OUT: u8 = 0xE0;
118pub const DBG_DIRECT: u8 = 0xF0;
autd3_firmware_emulator/fpga/params.rs

autd3_firmware_emulator/fpga/
params.rs
