autd3_firmware_emulator/cpu/
params.rs1pub const NANOSECONDS: u64 = 1;
2pub const MICROSECONDS: u64 = NANOSECONDS * 1000;
3pub const MILLISECONDS: u64 = MICROSECONDS * 1000;
4pub const SYS_TIME_TRANSITION_MARGIN: u64 = 10 * MILLISECONDS;
5
6pub const CPU_VERSION_MAJOR: u16 = 0xA2;
7pub const CPU_VERSION_MINOR: u16 = 0x01;
8
9pub const TRANS_NUM: usize = 249;
10
11pub const BRAM_SELECT_CONTROLLER: u8 = 0x0;
12pub const BRAM_SELECT_MOD: u8 = 0x1;
13pub const BRAM_SELECT_PWE_TABLE: u8 = 0x2;
14pub const BRAM_SELECT_STM: u8 = 0x3;
15
16pub const BRAM_CNT_SEL_MAIN: u8 = 0x00;
17pub const BRAM_CNT_SEL_PHASE_CORR: u8 = 0x01;
18pub const BRAM_CNT_SELECT_CLOCK: u8 = 0x02;
19
20pub const TRANSITION_MODE_SYNC_IDX: u8 = 0x00;
21pub const TRANSITION_MODE_SYS_TIME: u8 = 0x01;
22pub const TRANSITION_MODE_GPIO: u8 = 0x02;
23pub const TRANSITION_MODE_EXT: u8 = 0xF0;
24pub const TRANSITION_MODE_NONE: u8 = 0xFE;
25pub const TRANSITION_MODE_IMMEDIATE: u8 = 0xFF;
26
27pub const ADDR_CTL_FLAG: u16 = 0x00;
28pub const ADDR_FPGA_STATE: u16 = 0x01;
29pub const ADDR_VERSION_NUM_MAJOR: u16 = 0x02;
30pub const ADDR_VERSION_NUM_MINOR: u16 = 0x03;
31pub const ADDR_ECAT_SYNC_TIME_0: u16 = 0x10;
32pub const ADDR_ECAT_SYNC_TIME_1: u16 = 0x11;
33pub const ADDR_ECAT_SYNC_TIME_2: u16 = 0x12;
34pub const ADDR_ECAT_SYNC_TIME_3: u16 = 0x13;
35pub const ADDR_MOD_MEM_WR_SEGMENT: u16 = 0x20;
36pub const ADDR_MOD_REQ_RD_SEGMENT: u16 = 0x21;
37pub const ADDR_MOD_CYCLE0: u16 = 0x22;
38pub const ADDR_MOD_FREQ_DIV0: u16 = 0x23;
39pub const ADDR_MOD_REP0: u16 = 0x24;
40pub const ADDR_MOD_CYCLE1: u16 = 0x25;
41pub const ADDR_MOD_FREQ_DIV1: u16 = 0x26;
42pub const ADDR_MOD_REP1: u16 = 0x27;
43pub const ADDR_MOD_TRANSITION_MODE: u16 = 0x28;
44pub const ADDR_MOD_TRANSITION_VALUE_0: u16 = 0x29;
45pub const ADDR_MOD_TRANSITION_VALUE_1: u16 = 0x2A;
46pub const ADDR_MOD_TRANSITION_VALUE_2: u16 = 0x2B;
47pub const ADDR_MOD_TRANSITION_VALUE_3: u16 = 0x2C;
48pub const ADDR_SILENCER_FLAG: u16 = 0x40;
49pub const ADDR_SILENCER_UPDATE_RATE_INTENSITY: u16 = 0x41;
50pub const ADDR_SILENCER_UPDATE_RATE_PHASE: u16 = 0x42;
51pub const ADDR_SILENCER_COMPLETION_STEPS_INTENSITY: u16 = 0x43;
52pub const ADDR_SILENCER_COMPLETION_STEPS_PHASE: u16 = 0x44;
53pub const ADDR_STM_MEM_WR_SEGMENT: u16 = 0x50;
54pub const ADDR_STM_MEM_WR_PAGE: u16 = 0x51;
55pub const ADDR_STM_REQ_RD_SEGMENT: u16 = 0x52;
56pub const ADDR_STM_CYCLE0: u16 = 0x53;
57pub const ADDR_STM_FREQ_DIV0: u16 = 0x54;
58pub const ADDR_STM_REP0: u16 = 0x55;
59pub const ADDR_STM_MODE0: u16 = 0x56;
60pub const ADDR_STM_SOUND_SPEED0: u16 = 0x57;
61pub const ADDR_STM_NUM_FOCI0: u16 = 0x58;
62pub const ADDR_STM_CYCLE1: u16 = 0x59;
63pub const ADDR_STM_FREQ_DIV1: u16 = 0x5A;
64pub const ADDR_STM_REP1: u16 = 0x5B;
65pub const ADDR_STM_MODE1: u16 = 0x5C;
66pub const ADDR_STM_SOUND_SPEED1: u16 = 0x5D;
67pub const ADDR_STM_NUM_FOCI1: u16 = 0x5E;
68pub const ADDR_STM_TRANSITION_MODE: u16 = 0x5F;
69pub const ADDR_STM_TRANSITION_VALUE_0: u16 = 0x60;
70pub const ADDR_STM_TRANSITION_VALUE_1: u16 = 0x61;
71pub const ADDR_STM_TRANSITION_VALUE_2: u16 = 0x62;
72pub const ADDR_STM_TRANSITION_VALUE_3: u16 = 0x63;
73pub const ADDR_DEBUG_VALUE0_0: u16 = 0xF0;
74pub const ADDR_DEBUG_VALUE0_1: u16 = 0xF1;
75pub const ADDR_DEBUG_VALUE0_2: u16 = 0xF2;
76pub const ADDR_DEBUG_VALUE0_3: u16 = 0xF3;
77pub const ADDR_DEBUG_VALUE1_0: u16 = 0xF4;
78pub const ADDR_DEBUG_VALUE1_1: u16 = 0xF5;
79pub const ADDR_DEBUG_VALUE1_2: u16 = 0xF6;
80pub const ADDR_DEBUG_VALUE1_3: u16 = 0xF7;
81pub const ADDR_DEBUG_VALUE2_0: u16 = 0xF8;
82pub const ADDR_DEBUG_VALUE2_1: u16 = 0xF9;
83pub const ADDR_DEBUG_VALUE2_2: u16 = 0xFA;
84pub const ADDR_DEBUG_VALUE2_3: u16 = 0xFB;
85pub const ADDR_DEBUG_VALUE3_0: u16 = 0xFC;
86pub const ADDR_DEBUG_VALUE3_1: u16 = 0xFD;
87pub const ADDR_DEBUG_VALUE3_2: u16 = 0xFE;
88pub const ADDR_DEBUG_VALUE3_3: u16 = 0xFF;
89
90pub const CTL_FLAG_MOD_SET_BIT: u16 = 0;
91pub const CTL_FLAG_STM_SET_BIT: u16 = 1;
92pub const CTL_FLAG_SILENCER_SET_BIT: u16 = 2;
93pub const CTL_FLAG_DEBUG_SET_BIT: u16 = 4;
94pub const CTL_FLAG_SYNC_SET_BIT: u16 = 5;
95pub const CTL_FLAG_BIT_GPIO_IN_0: u16 = 8;
96pub const CTL_FLAG_BIT_GPIO_IN_1: u16 = 9;
97pub const CTL_FLAG_BIT_GPIO_IN_2: u16 = 10;
98pub const CTL_FLAG_BIT_GPIO_IN_3: u16 = 11;
99pub const CTL_FLAG_FORCE_FAN_BIT: u16 = 13;
100
101pub const CTL_FLAG_MOD_SET: u16 = 1 << CTL_FLAG_MOD_SET_BIT;
102pub const CTL_FLAG_STM_SET: u16 = 1 << CTL_FLAG_STM_SET_BIT;
103pub const CTL_FLAG_SILENCER_SET: u16 = 1 << CTL_FLAG_SILENCER_SET_BIT;
104pub const CTL_FLAG_DEBUG_SET: u16 = 1 << CTL_FLAG_DEBUG_SET_BIT;
105pub const CTL_FLAG_SYNC_SET: u16 = 1 << CTL_FLAG_SYNC_SET_BIT;
106pub const CTL_FLAG_GPIO_IN_0: u16 = 1 << CTL_FLAG_BIT_GPIO_IN_0;
107pub const CTL_FLAG_GPIO_IN_1: u16 = 1 << CTL_FLAG_BIT_GPIO_IN_1;
108pub const CTL_FLAG_GPIO_IN_2: u16 = 1 << CTL_FLAG_BIT_GPIO_IN_2;
109pub const CTL_FLAG_GPIO_IN_3: u16 = 1 << CTL_FLAG_BIT_GPIO_IN_3;
110pub const CTL_FLAG_FORCE_FAN: u16 = 1 << CTL_FLAG_FORCE_FAN_BIT;
111
112pub const FPGA_STATE_BIT_READS_FPGA_STATE_ENABLED: u8 = 7;
113pub const FPGA_STATE_READS_FPGA_STATE_ENABLED: u8 = 1 << FPGA_STATE_BIT_READS_FPGA_STATE_ENABLED;
114
115pub const STM_MODE_FOCUS: u16 = 0;
116pub const STM_MODE_GAIN: u16 = 1;
117
118pub const SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE: u8 = 0;
119pub const SILENCER_FLAG_BIT_PULSE_WIDTH: u8 = 1;
120pub const SILENCER_FLAG_FIXED_UPDATE_RATE_MODE: u8 = 1 << SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE;
121pub const SILENCER_FLAG_PULSE_WIDTH: u8 = 1 << SILENCER_FLAG_BIT_PULSE_WIDTH;
122pub const SILENCER_FLAG_STRICT_MODE: u8 = 1 << 2;
123
124pub const TAG_CLEAR: u8 = 0x01;
125pub const TAG_SYNC: u8 = 0x02;
126pub const TAG_FIRM_INFO: u8 = 0x03;
127pub const TAG_CONFIG_FPGA_CLK: u8 = 0x04;
128pub const TAG_MODULATION: u8 = 0x10;
129pub const TAG_MODULATION_CHANGE_SEGMENT: u8 = 0x11;
130pub const TAG_SILENCER: u8 = 0x21;
131pub const TAG_GAIN: u8 = 0x30;
132pub const TAG_GAIN_CHANGE_SEGMENT: u8 = 0x31;
133pub const TAG_GAIN_STM: u8 = 0x41;
134pub const TAG_FOCI_STM: u8 = 0x42;
135pub const TAG_GAIN_STM_CHANGE_SEGMENT: u8 = 0x43;
136pub const TAG_FOCI_STM_CHANGE_SEGMENT: u8 = 0x44;
137pub const TAG_FORCE_FAN: u8 = 0x60;
138pub const TAG_READS_FPGA_STATE: u8 = 0x61;
139pub const TAG_CONFIG_PULSE_WIDTH_ENCODER: u8 = 0x71;
140pub const TAG_PHASE_CORRECTION: u8 = 0x80;
141pub const TAG_DEBUG: u8 = 0xF0;
142pub const TAG_EMULATE_GPIO_IN: u8 = 0xF1;
143pub const TAG_CPU_GPIO_OUT: u8 = 0xF2;
144
145pub const INFO_TYPE_CPU_VERSION_MAJOR: u8 = 0x01;
146pub const INFO_TYPE_CPU_VERSION_MINOR: u8 = 0x02;
147pub const INFO_TYPE_FPGA_VERSION_MAJOR: u8 = 0x03;
148pub const INFO_TYPE_FPGA_VERSION_MINOR: u8 = 0x04;
149pub const INFO_TYPE_FPGA_FUNCTIONS: u8 = 0x05;
150pub const INFO_TYPE_CLEAR: u8 = 0x06;
151
152pub const GAIN_FLAG_UPDATE: u8 = 1 << 0;
153
154pub const MODULATION_FLAG_BEGIN: u8 = 1 << 0;
155pub const MODULATION_FLAG_END: u8 = 1 << 1;
156pub const MODULATION_FLAG_UPDATE: u8 = 1 << 2;
157pub const MODULATION_FLAG_SEGMENT: u8 = 1 << 3;
158
159pub const FOCI_STM_FLAG_BEGIN: u8 = 1 << 0;
160pub const FOCI_STM_FLAG_END: u8 = 1 << 1;
161pub const FOCI_STM_FLAG_UPDATE: u8 = 1 << 2;
162
163pub const GAIN_STM_FLAG_BEGIN: u8 = 1 << 0;
164pub const GAIN_STM_FLAG_END: u8 = 1 << 1;
165pub const GAIN_STM_FLAG_UPDATE: u8 = 1 << 2;
166pub const GAIN_STM_FLAG_SEGMENT: u8 = 1 << 3;
167
168pub const GAIN_STM_MODE_INTENSITY_PHASE_FULL: u8 = 0;
169pub const GAIN_STM_MODE_PHASE_FULL: u8 = 1;
170pub const GAIN_STM_MODE_PHASE_HALF: u8 = 2;
171
172pub const CLK_FLAG_BEGIN: u8 = 1 << 0;
173pub const CLK_FLAG_END: u8 = 1 << 1;
174
175pub const GPIO_IN_FLAG_0: u8 = 1 << 0;
176pub const GPIO_IN_FLAG_1: u8 = 1 << 1;
177pub const GPIO_IN_FLAG_2: u8 = 1 << 2;
178pub const GPIO_IN_FLAG_3: u8 = 1 << 3;
179
180pub const NO_ERR: u8 = 0x00;
181pub const ERR_BIT: u8 = 0x80;
182#[allow(clippy::identity_op)]
183pub const ERR_NOT_SUPPORTED_TAG: u8 = ERR_BIT | 0x00;
184pub const ERR_INVALID_MSG_ID: u8 = ERR_BIT | 0x01;
185pub const ERR_INVALID_INFO_TYPE: u8 = ERR_BIT | 0x04;
186pub const ERR_INVALID_GAIN_STM_MODE: u8 = ERR_BIT | 0x05;
187pub const ERR_INVALID_MODE: u8 = ERR_BIT | 0x07;
188pub const ERR_INVALID_SEGMENT_TRANSITION: u8 = ERR_BIT | 0x08;
189pub const ERR_INVALID_PWE_DATA_SIZE: u8 = ERR_BIT | 0x09;
190pub const ERR_MISS_TRANSITION_TIME: u8 = ERR_BIT | 0x0B;
191pub const ERR_CLK_INCOMPLETE_DATA: u8 = ERR_BIT | 0x0D;
192pub const ERR_INVALID_SILENCER_SETTING: u8 = ERR_BIT | 0x0E;
193pub const ERR_INVALID_TRANSITION_MODE: u8 = ERR_BIT | 0x0F;