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pub const CPU_VERSION_MAJOR: u16 = 0x8F;
pub const CPU_VERSION_MINOR: u16 = 0x00;

pub const TRANS_NUM: usize = 249;

pub const BRAM_SELECT_CONTROLLER: u8 = 0x0;
pub const BRAM_SELECT_MOD: u8 = 0x1;
pub const BRAM_SELECT_DUTY_TABLE: u8 = 0x2;
pub const BRAM_SELECT_STM: u8 = 0x3;

pub const BRAM_CNT_SEL_MAIN: u8 = 0x00;
pub const BRAM_CNT_SEL_FILTER: u8 = 0x01;

pub const BRAM_ADDR_CTL_FLAG: u16 = 0x00;
pub const BRAM_ADDR_FPGA_STATE: u16 = 0x01;
pub const BRAM_ADDR_ECAT_SYNC_TIME_0: u16 = 0x11;
pub const BRAM_ADDR_ECAT_SYNC_TIME_1: u16 = BRAM_ADDR_ECAT_SYNC_TIME_0 + 1;
pub const BRAM_ADDR_ECAT_SYNC_TIME_2: u16 = BRAM_ADDR_ECAT_SYNC_TIME_0 + 2;
pub const BRAM_ADDR_ECAT_SYNC_TIME_3: u16 = BRAM_ADDR_ECAT_SYNC_TIME_0 + 3;
pub const BRAM_ADDR_MOD_MEM_WR_SEGMENT: u16 = 0x20;
pub const BRAM_ADDR_MOD_REQ_RD_SEGMENT: u16 = 0x21;
pub const BRAM_ADDR_MOD_CYCLE_0: u16 = 0x22;
pub const BRAM_ADDR_MOD_FREQ_DIV_0_0: u16 = 0x23;
pub const BRAM_ADDR_MOD_FREQ_DIV_0_1: u16 = 0x24;
pub const BRAM_ADDR_MOD_CYCLE_1: u16 = 0x25;
pub const BRAM_ADDR_MOD_FREQ_DIV_1_0: u16 = 0x26;
pub const BRAM_ADDR_MOD_FREQ_DIV_1_1: u16 = 0x27;
pub const BRAM_ADDR_MOD_REP_0_0: u16 = 0x28;
pub const BRAM_ADDR_MOD_REP_0_1: u16 = 0x29;
pub const BRAM_ADDR_MOD_REP_1_0: u16 = 0x2A;
pub const BRAM_ADDR_MOD_REP_1_1: u16 = 0x2B;
pub const BRAM_ADDR_VERSION_NUM_MAJOR: u16 = 0x30;
pub const BRAM_ADDR_VERSION_NUM_MINOR: u16 = 0x31;
pub const BRAM_ADDR_SILENCER_MODE: u16 = 0x40;
pub const BRAM_ADDR_SILENCER_UPDATE_RATE_INTENSITY: u16 = 0x41;
pub const BRAM_ADDR_SILENCER_UPDATE_RATE_PHASE: u16 = 0x42;
pub const BRAM_ADDR_SILENCER_COMPLETION_STEPS_INTENSITY: u16 = 0x43;
pub const BRAM_ADDR_SILENCER_COMPLETION_STEPS_PHASE: u16 = 0x44;
pub const BRAM_ADDR_STM_MEM_WR_SEGMENT: u16 = 0x50;
pub const BRAM_ADDR_STM_MEM_WR_PAGE: u16 = 0x51;
pub const BRAM_ADDR_STM_REQ_RD_SEGMENT: u16 = 0x52;
pub const BRAM_ADDR_STM_CYCLE_0: u16 = 0x54;
pub const BRAM_ADDR_STM_FREQ_DIV_0_0: u16 = 0x55;
pub const BRAM_ADDR_STM_FREQ_DIV_0_1: u16 = 0x56;
pub const BRAM_ADDR_STM_CYCLE_1: u16 = 0x57;
pub const BRAM_ADDR_STM_FREQ_DIV_1_0: u16 = 0x58;
pub const BRAM_ADDR_STM_FREQ_DIV_1_1: u16 = 0x59;
pub const BRAM_ADDR_STM_REP_0_0: u16 = 0x5A;
pub const BRAM_ADDR_STM_REP_0_1: u16 = 0x5B;
pub const BRAM_ADDR_STM_REP_1_0: u16 = 0x5C;
pub const BRAM_ADDR_STM_REP_1_1: u16 = 0x5D;
pub const BRAM_ADDR_STM_MODE_0: u16 = 0x5E;
pub const BRAM_ADDR_STM_MODE_1: u16 = 0x5F;
pub const BRAM_ADDR_STM_SOUND_SPEED_0_0: u16 = 0x60;
pub const BRAM_ADDR_STM_SOUND_SPEED_0_1: u16 = 0x61;
pub const BRAM_ADDR_STM_SOUND_SPEED_1_0: u16 = 0x62;
pub const BRAM_ADDR_STM_SOUND_SPEED_1_1: u16 = 0x63;
pub const BRAM_ADDR_PULSE_WIDTH_ENCODER_TABLE_WR_PAGE: u16 = 0xE0;
pub const BRAM_ADDR_PULSE_WIDTH_ENCODER_FULL_WIDTH_START: u16 = 0xE1;
pub const BRAM_ADDR_DEBUG_OUT_IDX: u16 = 0xF0;

pub const CTL_FLAG_MOD_SET_BIT: u16 = 0;
pub const CTL_FLAG_STM_SET_BIT: u16 = 1;
pub const CTL_FLAG_SILENCER_SET_BIT: u16 = 2;
pub const CTL_FLAG_PULSE_WIDTH_ENCODER_SET_BIT: u16 = 3;
pub const CTL_FLAG_DEBUG_SET_BIT: u16 = 4;
pub const CTL_FLAG_SYNC_SET_BIT: u16 = 5;
pub const CTL_FLAG_FORCE_FAN_BIT: u16 = 13;

pub const CTL_FLAG_MOD_SET: u16 = 1 << CTL_FLAG_MOD_SET_BIT;
pub const CTL_FLAG_STM_SET: u16 = 1 << CTL_FLAG_STM_SET_BIT;
pub const CTL_FLAG_SILENCER_SET: u16 = 1 << CTL_FLAG_SILENCER_SET_BIT;
pub const CTL_FLAG_PULSE_WIDTH_ENCODER_SET: u16 = 1 << CTL_FLAG_PULSE_WIDTH_ENCODER_SET_BIT;
pub const CTL_FLAG_DEBUG_SET: u16 = 1 << CTL_FLAG_DEBUG_SET_BIT;
pub const CTL_FLAG_SYNC_SET: u16 = 1 << CTL_FLAG_SYNC_SET_BIT;
pub const CTL_FLAG_FORCE_FAN: u16 = 1 << CTL_FLAG_FORCE_FAN_BIT;

pub const READS_FPGA_STATE_ENABLED_BIT: u8 = 7;
pub const READS_FPGA_STATE_ENABLED: u8 = 1 << READS_FPGA_STATE_ENABLED_BIT;

pub const STM_MODE_FOCUS: u16 = 0;
pub const STM_MODE_GAIN: u16 = 1;

pub const SILNCER_MODE_FIXED_COMPLETION_STEPS: u16 = 0;
pub const SILNCER_MODE_FIXED_UPDATE_RATE: u16 = 1;
pub const SILNCER_FLAG_MODE: u8 = 1 << 0;
pub const SILNCER_FLAG_STRICT_MODE: u8 = 1 << 1;

pub const TAG_CLEAR: u8 = 0x01;
pub const TAG_SYNC: u8 = 0x02;
pub const TAG_FIRM_INFO: u8 = 0x03;
pub const TAG_MODULATION: u8 = 0x10;
pub const TAG_MODULATION_CHANGE_SEGMENT: u8 = 0x11;
pub const TAG_SILENCER: u8 = 0x20;
pub const TAG_GAIN: u8 = 0x30;
pub const TAG_GAIN_CHANGE_SEGMENT: u8 = 0x31;
pub const TAG_FOCUS_STM: u8 = 0x40;
pub const TAG_GAIN_STM: u8 = 0x41;
pub const TAG_FOCUS_STM_CHANGE_SEGMENT: u8 = 0x42;
pub const TAG_GAIN_STM_CHANGE_SEGMENT: u8 = 0x43;
pub const TAG_FORCE_FAN: u8 = 0x60;
pub const TAG_READS_FPGA_STATE: u8 = 0x61;
pub const TAG_CONFIG_PULSE_WIDTH_ENCODER: u8 = 0x70;
pub const TAG_PHASE_FILTER: u8 = 0x80;
pub const TAG_DEBUG: u8 = 0xF0;

pub const INFO_TYPE_CPU_VERSION_MAJOR: u8 = 0x01;
pub const INFO_TYPE_CPU_VERSION_MINOR: u8 = 0x02;
pub const INFO_TYPE_FPGA_VERSION_MAJOR: u8 = 0x03;
pub const INFO_TYPE_FPGA_VERSION_MINOR: u8 = 0x04;
pub const INFO_TYPE_FPGA_FUNCTIONS: u8 = 0x05;
pub const INFO_TYPE_CLEAR: u8 = 0x06;

pub const GAIN_FLAG_UPDATE: u16 = 1 << 0;

pub const MODULATION_FLAG_BEGIN: u8 = 1 << 0;
pub const MODULATION_FLAG_END: u8 = 1 << 1;
pub const MODULATION_FLAG_UPDATE: u8 = 1 << 2;

pub const FOCUS_STM_FLAG_BEGIN: u8 = 1 << 0;
pub const FOCUS_STM_FLAG_END: u8 = 1 << 1;
pub const FOCUS_STM_FLAG_UPDATE: u8 = 1 << 2;

pub const GAIN_STM_FLAG_BEGIN: u8 = 1 << 2;
pub const GAIN_STM_FLAG_END: u8 = 1 << 3;
pub const GAIN_STM_FLAG_UPDATE: u8 = 1 << 4;

pub const GAIN_STM_MODE_INTENSITY_PHASE_FULL: u8 = 0;
pub const GAIN_STM_MODE_PHASE_FULL: u8 = 1;
pub const GAIN_STM_MODE_PHASE_HALF: u8 = 2;

pub const PULSE_WIDTH_ENCODER_FLAG_BEGIN: u8 = 1 << 0;
pub const PULSE_WIDTH_ENCODER_FLAG_END: u8 = 1 << 1;

pub const NO_ERR: u8 = 0x00;
pub const ERR_BIT: u8 = 0x80;
#[allow(clippy::identity_op)]
pub const ERR_NOT_SUPPORTED_TAG: u8 = ERR_BIT | 0x00;
pub const ERR_INVALID_MSG_ID: u8 = ERR_BIT | 0x01;
pub const ERR_FREQ_DIV_TOO_SMALL: u8 = ERR_BIT | 0x02;
pub const ERR_COMPLETION_STEPS_TOO_LARGE: u8 = ERR_BIT | 0x03;
pub const ERR_INVALID_INFO_TYPE: u8 = ERR_BIT | 0x04;
pub const ERR_INVALID_GAIN_STM_MODE: u8 = ERR_BIT | 0x05;
pub const ERR_INVALID_SEGMENT: u8 = ERR_BIT | 0x06;
pub const ERR_INVALID_MODE: u8 = ERR_BIT | 0x07;
pub const ERR_INVALID_SEGMENT_TRANSITION: u8 = ERR_BIT | 0x08;
pub const ERR_INVALID_PWE_DATA_SIZE: u8 = ERR_BIT | 0x09;
pub const ERR_PWE_INCOMPLETE_DATA: u8 = ERR_BIT | 0x0A;