autd3_cpu_wire/
params.rs

1// AUTO-GENERATED by `cargo xtask cpu gen-param` from
2// firmware/fpga/rtl/sources_1/new/headers/params.svh and the IP .xci files. DO NOT EDIT.
3// Client-facing wire constants shared with the firmware.
4
5pub const NUM_TRANSDUCERS: usize = 249;
6pub const NUM_BANKS: usize = 2;
7pub const EMISSION_MAX_INDICES: u32 = 1024;
8pub const EMISSION_SLOT_WORDS: usize = 256;
9pub const FOCUS_WORDS: usize = 4;
10pub const NUM_FOCI_MAX: u8 = 8;
11pub const ULTRASOUND_FREQ_HZ: u32 = 40000;
12pub const REP_INFINITE: u16 = 0xFFFF;
13pub const FUNC_DYNAMIC_FREQ_BIT: u16 = 1;
14pub const FUNC_FLASH_OTA_BIT: u16 = 2;
15pub const FUNC_EMULATOR_BIT: u16 = 7;
16pub const FLASH_WRITABLE_BASE: u32 = 0x80_0000;
17pub const FLASH_END: u32 = 0x100_0000;
18pub const FLASH_IMAGE_BASE: u32 = 0x80_0100;
19pub const FLASH_USR_ACCESS_GOLDEN: u32 = 0x474F_4C44;
20pub const FLASH_USR_ACCESS_UPDATE: u32 = 0x5550_4454;
21pub const VERSION_NUM_MAJOR: u8 = 0x0;
22pub const VERSION_NUM_MINOR: u8 = 0x9;
23pub const VERSION_NUM_PATCH: u8 = 0x0;
24
25pub const FPGA_STATE_BIT_THERMAL_ASSERT: u16 = 0;
26pub const FPGA_STATE_THERMAL_ASSERT: u16 = 1 << FPGA_STATE_BIT_THERMAL_ASSERT;
27pub const FPGA_STATE_BIT_MOD_BANK: u16 = 1;
28pub const FPGA_STATE_MOD_BANK: u16 = 1 << FPGA_STATE_BIT_MOD_BANK;
29pub const FPGA_STATE_BIT_PATTERN_BANK: u16 = 2;
30pub const FPGA_STATE_PATTERN_BANK: u16 = 1 << FPGA_STATE_BIT_PATTERN_BANK;
31pub const FPGA_STATE_BIT_PATTERN_MODE: u16 = 3;
32pub const FPGA_STATE_PATTERN_MODE: u16 = 1 << FPGA_STATE_BIT_PATTERN_MODE;
33pub const FPGA_STATE_BIT_PATTERN_STOPPED: u16 = 4;
34pub const FPGA_STATE_PATTERN_STOPPED: u16 = 1 << FPGA_STATE_BIT_PATTERN_STOPPED;
35pub const FPGA_STATE_BIT_MOD_STOPPED: u16 = 5;
36pub const FPGA_STATE_MOD_STOPPED: u16 = 1 << FPGA_STATE_BIT_MOD_STOPPED;
37pub const FPGA_STATE_BIT_TRANSITION_PENDING: u16 = 6;
38pub const FPGA_STATE_TRANSITION_PENDING: u16 = 1 << FPGA_STATE_BIT_TRANSITION_PENDING;
39pub const FPGA_STATE_BIT_READS_ENABLED: u16 = 7;
40pub const FPGA_STATE_READS_ENABLED: u16 = 1 << FPGA_STATE_BIT_READS_ENABLED;
41
42pub const TRANSITION_MODE_SYNC_IDX: u8 = 0x0;
43pub const TRANSITION_MODE_SYS_TIME: u8 = 0x1;
44pub const TRANSITION_MODE_GPIO: u8 = 0x2;
45pub const TRANSITION_MODE_EXT: u8 = 0xF0;
46pub const TRANSITION_MODE_IMMEDIATE: u8 = 0xFF;
47
48pub const EMISSION_TYPE_FOCI: u8 = 0x0;
49pub const EMISSION_TYPE_RAW: u8 = 0x1;
50
51pub const SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE: u8 = 0;
52pub const SILENCER_FLAG_FIXED_UPDATE_RATE_MODE: u8 = 1 << SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE;
53
54pub const GPIO_O_TYPE_NONE: u8 = 0x0;
55pub const GPIO_O_TYPE_BASE_SIG: u8 = 0x1;
56pub const GPIO_O_TYPE_THERMO: u8 = 0x2;
57pub const GPIO_O_TYPE_FORCE_FAN: u8 = 0x3;
58pub const GPIO_O_TYPE_SYNC: u8 = 0x10;
59pub const GPIO_O_TYPE_MOD_BANK: u8 = 0x20;
60pub const GPIO_O_TYPE_MOD_IDX: u8 = 0x21;
61pub const GPIO_O_TYPE_PATTERN_BANK: u8 = 0x50;
62pub const GPIO_O_TYPE_PATTERN_IDX: u8 = 0x51;
63pub const GPIO_O_TYPE_IS_STM_MODE: u8 = 0x52;
64pub const GPIO_O_TYPE_SYS_TIME_EQ: u8 = 0x60;
65pub const GPIO_O_TYPE_SYNC_DIFF: u8 = 0x70;
66pub const GPIO_O_TYPE_PWM_OUT: u8 = 0xE0;
67pub const GPIO_O_TYPE_DIRECT: u8 = 0xF0;
68
69pub const MOD_BUFFER_SAMPLES: usize = 65536;
70pub const PWE_TABLE_SIZE: usize = 256;
71
72pub const FOCUS_TR_X_MAX: i32 = 6909;
73pub const FOCUS_TR_Y_MAX: i32 = 5283;
74
75pub const FPGA_CLK_FREQ_HZ: u32 = 20_480_000;
autd3_cpu_wire/params.rs

autd3_cpu_wire/
params.rs
