autd3_core/firmware/
segment.rs

1/// Segment of the FPGA memory
2#[derive(Default, Debug, Copy, Clone, PartialEq, Eq, Hash)]
3#[repr(u8)]
4pub enum Segment {
5    /// Segment 0
6    #[default]
7    S0 = 0,
8    /// Segment 1
9    S1 = 1,
10}