#[repr(C)]
pub struct RegisterBlock {
Show 17 fields pub aes_cr: Reg<AES_CR_SPEC>, pub aes_mr: Reg<AES_MR_SPEC>, pub aes_ier: Reg<AES_IER_SPEC>, pub aes_idr: Reg<AES_IDR_SPEC>, pub aes_imr: Reg<AES_IMR_SPEC>, pub aes_isr: Reg<AES_ISR_SPEC>, pub aes_keywr: [Reg<AES_KEYWR_SPEC>; 8], pub aes_idatar: [Reg<AES_IDATAR_SPEC>; 4], pub aes_odatar: [Reg<AES_ODATAR_SPEC>; 4], pub aes_ivr: [Reg<AES_IVR_SPEC>; 4], pub aes_aadlenr: Reg<AES_AADLENR_SPEC>, pub aes_clenr: Reg<AES_CLENR_SPEC>, pub aes_ghashr: [Reg<AES_GHASHR_SPEC>; 4], pub aes_tagr: [Reg<AES_TAGR_SPEC>; 4], pub aes_ctrr: Reg<AES_CTRR_SPEC>, pub aes_gcmhr: [Reg<AES_GCMHR_SPEC>; 4], pub aes_version: Reg<AES_VERSION_SPEC>, /* private fields */
}
Expand description

Register block

Fields

aes_cr: Reg<AES_CR_SPEC>

0x00 - Control Register

aes_mr: Reg<AES_MR_SPEC>

0x04 - Mode Register

aes_ier: Reg<AES_IER_SPEC>

0x10 - Interrupt Enable Register

aes_idr: Reg<AES_IDR_SPEC>

0x14 - Interrupt Disable Register

aes_imr: Reg<AES_IMR_SPEC>

0x18 - Interrupt Mask Register

aes_isr: Reg<AES_ISR_SPEC>

0x1c - Interrupt Status Register

aes_keywr: [Reg<AES_KEYWR_SPEC>; 8]

0x20..0x40 - Key Word Register 0

aes_idatar: [Reg<AES_IDATAR_SPEC>; 4]

0x40..0x50 - Input Data Register 0

aes_odatar: [Reg<AES_ODATAR_SPEC>; 4]

0x50..0x60 - Output Data Register 0

aes_ivr: [Reg<AES_IVR_SPEC>; 4]

0x60..0x70 - Initialization Vector Register 0

aes_aadlenr: Reg<AES_AADLENR_SPEC>

0x70 - Additional Authenticated Data Length Register

aes_clenr: Reg<AES_CLENR_SPEC>

0x74 - Plaintext/Ciphertext Length Register

aes_ghashr: [Reg<AES_GHASHR_SPEC>; 4]

0x78..0x88 - GCM Intermediate Hash Word Register 0

aes_tagr: [Reg<AES_TAGR_SPEC>; 4]

0x88..0x98 - GCM Authentication Tag Word Register 0

aes_ctrr: Reg<AES_CTRR_SPEC>

0x98 - GCM Encryption Counter Value Register

aes_gcmhr: [Reg<AES_GCMHR_SPEC>; 4]

0x9c..0xac - GCM H Word Register 0

aes_version: Reg<AES_VERSION_SPEC>

0xfc - Version Register

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