atsamv71n21/usbhs/
usbhs_hstpipier.rs

1#[doc = "Register `USBHS_HSTPIPIER[%s]` writer"]
2pub struct W(crate::W<USBHS_HSTPIPIER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<USBHS_HSTPIPIER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<USBHS_HSTPIPIER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<USBHS_HSTPIPIER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RXINES` writer - Received IN Data Interrupt Enable"]
23pub struct RXINES_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> RXINES_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `TXOUTES` writer - Transmitted OUT Data Interrupt Enable"]
45pub struct TXOUTES_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> TXOUTES_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63        self.w
64    }
65}
66#[doc = "Field `TXSTPES` writer - Transmitted SETUP Interrupt Enable"]
67pub struct TXSTPES_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> TXSTPES_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
85        self.w
86    }
87}
88#[doc = "Field `PERRES` writer - Pipe Error Interrupt Enable"]
89pub struct PERRES_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> PERRES_W<'a> {
93    #[doc = r"Sets the field bit"]
94    #[inline(always)]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r"Clears the field bit"]
99    #[inline(always)]
100    pub fn clear_bit(self) -> &'a mut W {
101        self.bit(false)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub fn bit(self, value: bool) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
107        self.w
108    }
109}
110#[doc = "Field `NAKEDES` writer - NAKed Interrupt Enable"]
111pub struct NAKEDES_W<'a> {
112    w: &'a mut W,
113}
114impl<'a> NAKEDES_W<'a> {
115    #[doc = r"Sets the field bit"]
116    #[inline(always)]
117    pub fn set_bit(self) -> &'a mut W {
118        self.bit(true)
119    }
120    #[doc = r"Clears the field bit"]
121    #[inline(always)]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r"Writes raw bits to the field"]
126    #[inline(always)]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
129        self.w
130    }
131}
132#[doc = "Field `OVERFIES` writer - Overflow Interrupt Enable"]
133pub struct OVERFIES_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> OVERFIES_W<'a> {
137    #[doc = r"Sets the field bit"]
138    #[inline(always)]
139    pub fn set_bit(self) -> &'a mut W {
140        self.bit(true)
141    }
142    #[doc = r"Clears the field bit"]
143    #[inline(always)]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r"Writes raw bits to the field"]
148    #[inline(always)]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
151        self.w
152    }
153}
154#[doc = "Field `RXSTALLDES` writer - Received STALLed Interrupt Enable"]
155pub struct RXSTALLDES_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> RXSTALLDES_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
173        self.w
174    }
175}
176#[doc = "Field `SHORTPACKETIES` writer - Short Packet Interrupt Enable"]
177pub struct SHORTPACKETIES_W<'a> {
178    w: &'a mut W,
179}
180impl<'a> SHORTPACKETIES_W<'a> {
181    #[doc = r"Sets the field bit"]
182    #[inline(always)]
183    pub fn set_bit(self) -> &'a mut W {
184        self.bit(true)
185    }
186    #[doc = r"Clears the field bit"]
187    #[inline(always)]
188    pub fn clear_bit(self) -> &'a mut W {
189        self.bit(false)
190    }
191    #[doc = r"Writes raw bits to the field"]
192    #[inline(always)]
193    pub fn bit(self, value: bool) -> &'a mut W {
194        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
195        self.w
196    }
197}
198#[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Enable"]
199pub struct NBUSYBKES_W<'a> {
200    w: &'a mut W,
201}
202impl<'a> NBUSYBKES_W<'a> {
203    #[doc = r"Sets the field bit"]
204    #[inline(always)]
205    pub fn set_bit(self) -> &'a mut W {
206        self.bit(true)
207    }
208    #[doc = r"Clears the field bit"]
209    #[inline(always)]
210    pub fn clear_bit(self) -> &'a mut W {
211        self.bit(false)
212    }
213    #[doc = r"Writes raw bits to the field"]
214    #[inline(always)]
215    pub fn bit(self, value: bool) -> &'a mut W {
216        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
217        self.w
218    }
219}
220#[doc = "Field `PDISHDMAS` writer - Pipe Interrupts Disable HDMA Request Enable"]
221pub struct PDISHDMAS_W<'a> {
222    w: &'a mut W,
223}
224impl<'a> PDISHDMAS_W<'a> {
225    #[doc = r"Sets the field bit"]
226    #[inline(always)]
227    pub fn set_bit(self) -> &'a mut W {
228        self.bit(true)
229    }
230    #[doc = r"Clears the field bit"]
231    #[inline(always)]
232    pub fn clear_bit(self) -> &'a mut W {
233        self.bit(false)
234    }
235    #[doc = r"Writes raw bits to the field"]
236    #[inline(always)]
237    pub fn bit(self, value: bool) -> &'a mut W {
238        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
239        self.w
240    }
241}
242#[doc = "Field `PFREEZES` writer - Pipe Freeze Enable"]
243pub struct PFREEZES_W<'a> {
244    w: &'a mut W,
245}
246impl<'a> PFREEZES_W<'a> {
247    #[doc = r"Sets the field bit"]
248    #[inline(always)]
249    pub fn set_bit(self) -> &'a mut W {
250        self.bit(true)
251    }
252    #[doc = r"Clears the field bit"]
253    #[inline(always)]
254    pub fn clear_bit(self) -> &'a mut W {
255        self.bit(false)
256    }
257    #[doc = r"Writes raw bits to the field"]
258    #[inline(always)]
259    pub fn bit(self, value: bool) -> &'a mut W {
260        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
261        self.w
262    }
263}
264#[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"]
265pub struct RSTDTS_W<'a> {
266    w: &'a mut W,
267}
268impl<'a> RSTDTS_W<'a> {
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
283        self.w
284    }
285}
286impl W {
287    #[doc = "Bit 0 - Received IN Data Interrupt Enable"]
288    #[inline(always)]
289    pub fn rxines(&mut self) -> RXINES_W {
290        RXINES_W { w: self }
291    }
292    #[doc = "Bit 1 - Transmitted OUT Data Interrupt Enable"]
293    #[inline(always)]
294    pub fn txoutes(&mut self) -> TXOUTES_W {
295        TXOUTES_W { w: self }
296    }
297    #[doc = "Bit 2 - Transmitted SETUP Interrupt Enable"]
298    #[inline(always)]
299    pub fn txstpes(&mut self) -> TXSTPES_W {
300        TXSTPES_W { w: self }
301    }
302    #[doc = "Bit 3 - Pipe Error Interrupt Enable"]
303    #[inline(always)]
304    pub fn perres(&mut self) -> PERRES_W {
305        PERRES_W { w: self }
306    }
307    #[doc = "Bit 4 - NAKed Interrupt Enable"]
308    #[inline(always)]
309    pub fn nakedes(&mut self) -> NAKEDES_W {
310        NAKEDES_W { w: self }
311    }
312    #[doc = "Bit 5 - Overflow Interrupt Enable"]
313    #[inline(always)]
314    pub fn overfies(&mut self) -> OVERFIES_W {
315        OVERFIES_W { w: self }
316    }
317    #[doc = "Bit 6 - Received STALLed Interrupt Enable"]
318    #[inline(always)]
319    pub fn rxstalldes(&mut self) -> RXSTALLDES_W {
320        RXSTALLDES_W { w: self }
321    }
322    #[doc = "Bit 7 - Short Packet Interrupt Enable"]
323    #[inline(always)]
324    pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W {
325        SHORTPACKETIES_W { w: self }
326    }
327    #[doc = "Bit 12 - Number of Busy Banks Enable"]
328    #[inline(always)]
329    pub fn nbusybkes(&mut self) -> NBUSYBKES_W {
330        NBUSYBKES_W { w: self }
331    }
332    #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Enable"]
333    #[inline(always)]
334    pub fn pdishdmas(&mut self) -> PDISHDMAS_W {
335        PDISHDMAS_W { w: self }
336    }
337    #[doc = "Bit 17 - Pipe Freeze Enable"]
338    #[inline(always)]
339    pub fn pfreezes(&mut self) -> PFREEZES_W {
340        PFREEZES_W { w: self }
341    }
342    #[doc = "Bit 18 - Reset Data Toggle Enable"]
343    #[inline(always)]
344    pub fn rstdts(&mut self) -> RSTDTS_W {
345        RSTDTS_W { w: self }
346    }
347    #[doc = "Writes raw bits to the register."]
348    #[inline(always)]
349    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
350        self.0.bits(bits);
351        self
352    }
353}
354#[doc = "Host Pipe Enable Register (n = 0) 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usbhs_hstpipier](index.html) module"]
355pub struct USBHS_HSTPIPIER_SPEC;
356impl crate::RegisterSpec for USBHS_HSTPIPIER_SPEC {
357    type Ux = u32;
358}
359#[doc = "`write(|w| ..)` method takes [usbhs_hstpipier::W](W) writer structure"]
360impl crate::Writable for USBHS_HSTPIPIER_SPEC {
361    type Writer = W;
362}
363#[doc = "`reset()` method sets USBHS_HSTPIPIER[%s]
364to value 0"]
365impl crate::Resettable for USBHS_HSTPIPIER_SPEC {
366    #[inline(always)]
367    fn reset_value() -> Self::Ux {
368        0
369    }
370}
atsamv71n21/usbhs/usbhs_hstpipier.rs

atsamv71n21/usbhs/
usbhs_hstpipier.rs
