atsamv71n21/gmac/
gmac_st1rpq.rs1#[doc = "Register `GMAC_ST1RPQ[%s]` reader"]
2pub struct R(crate::R<GMAC_ST1RPQ_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<GMAC_ST1RPQ_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<GMAC_ST1RPQ_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<GMAC_ST1RPQ_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `GMAC_ST1RPQ[%s]` writer"]
17pub struct W(crate::W<GMAC_ST1RPQ_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<GMAC_ST1RPQ_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<GMAC_ST1RPQ_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<GMAC_ST1RPQ_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `QNB` reader - Queue Number (0-2)"]
38pub struct QNB_R(crate::FieldReader<u8, u8>);
39impl QNB_R {
40 #[inline(always)]
41 pub(crate) fn new(bits: u8) -> Self {
42 QNB_R(crate::FieldReader::new(bits))
43 }
44}
45impl core::ops::Deref for QNB_R {
46 type Target = crate::FieldReader<u8, u8>;
47 #[inline(always)]
48 fn deref(&self) -> &Self::Target {
49 &self.0
50 }
51}
52#[doc = "Field `QNB` writer - Queue Number (0-2)"]
53pub struct QNB_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> QNB_W<'a> {
57 #[doc = r"Writes raw bits to the field"]
58 #[inline(always)]
59 pub unsafe fn bits(self, value: u8) -> &'a mut W {
60 self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
61 self.w
62 }
63}
64#[doc = "Field `DSTCM` reader - Differentiated Services or Traffic Class Match"]
65pub struct DSTCM_R(crate::FieldReader<u8, u8>);
66impl DSTCM_R {
67 #[inline(always)]
68 pub(crate) fn new(bits: u8) -> Self {
69 DSTCM_R(crate::FieldReader::new(bits))
70 }
71}
72impl core::ops::Deref for DSTCM_R {
73 type Target = crate::FieldReader<u8, u8>;
74 #[inline(always)]
75 fn deref(&self) -> &Self::Target {
76 &self.0
77 }
78}
79#[doc = "Field `DSTCM` writer - Differentiated Services or Traffic Class Match"]
80pub struct DSTCM_W<'a> {
81 w: &'a mut W,
82}
83impl<'a> DSTCM_W<'a> {
84 #[doc = r"Writes raw bits to the field"]
85 #[inline(always)]
86 pub unsafe fn bits(self, value: u8) -> &'a mut W {
87 self.w.bits = (self.w.bits & !(0xff << 4)) | ((value as u32 & 0xff) << 4);
88 self.w
89 }
90}
91#[doc = "Field `UDPM` reader - UDP Port Match"]
92pub struct UDPM_R(crate::FieldReader<u16, u16>);
93impl UDPM_R {
94 #[inline(always)]
95 pub(crate) fn new(bits: u16) -> Self {
96 UDPM_R(crate::FieldReader::new(bits))
97 }
98}
99impl core::ops::Deref for UDPM_R {
100 type Target = crate::FieldReader<u16, u16>;
101 #[inline(always)]
102 fn deref(&self) -> &Self::Target {
103 &self.0
104 }
105}
106#[doc = "Field `UDPM` writer - UDP Port Match"]
107pub struct UDPM_W<'a> {
108 w: &'a mut W,
109}
110impl<'a> UDPM_W<'a> {
111 #[doc = r"Writes raw bits to the field"]
112 #[inline(always)]
113 pub unsafe fn bits(self, value: u16) -> &'a mut W {
114 self.w.bits = (self.w.bits & !(0xffff << 12)) | ((value as u32 & 0xffff) << 12);
115 self.w
116 }
117}
118#[doc = "Field `DSTCE` reader - Differentiated Services or Traffic Class Match Enable"]
119pub struct DSTCE_R(crate::FieldReader<bool, bool>);
120impl DSTCE_R {
121 #[inline(always)]
122 pub(crate) fn new(bits: bool) -> Self {
123 DSTCE_R(crate::FieldReader::new(bits))
124 }
125}
126impl core::ops::Deref for DSTCE_R {
127 type Target = crate::FieldReader<bool, bool>;
128 #[inline(always)]
129 fn deref(&self) -> &Self::Target {
130 &self.0
131 }
132}
133#[doc = "Field `DSTCE` writer - Differentiated Services or Traffic Class Match Enable"]
134pub struct DSTCE_W<'a> {
135 w: &'a mut W,
136}
137impl<'a> DSTCE_W<'a> {
138 #[doc = r"Sets the field bit"]
139 #[inline(always)]
140 pub fn set_bit(self) -> &'a mut W {
141 self.bit(true)
142 }
143 #[doc = r"Clears the field bit"]
144 #[inline(always)]
145 pub fn clear_bit(self) -> &'a mut W {
146 self.bit(false)
147 }
148 #[doc = r"Writes raw bits to the field"]
149 #[inline(always)]
150 pub fn bit(self, value: bool) -> &'a mut W {
151 self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
152 self.w
153 }
154}
155#[doc = "Field `UDPE` reader - UDP Port Match Enable"]
156pub struct UDPE_R(crate::FieldReader<bool, bool>);
157impl UDPE_R {
158 #[inline(always)]
159 pub(crate) fn new(bits: bool) -> Self {
160 UDPE_R(crate::FieldReader::new(bits))
161 }
162}
163impl core::ops::Deref for UDPE_R {
164 type Target = crate::FieldReader<bool, bool>;
165 #[inline(always)]
166 fn deref(&self) -> &Self::Target {
167 &self.0
168 }
169}
170#[doc = "Field `UDPE` writer - UDP Port Match Enable"]
171pub struct UDPE_W<'a> {
172 w: &'a mut W,
173}
174impl<'a> UDPE_W<'a> {
175 #[doc = r"Sets the field bit"]
176 #[inline(always)]
177 pub fn set_bit(self) -> &'a mut W {
178 self.bit(true)
179 }
180 #[doc = r"Clears the field bit"]
181 #[inline(always)]
182 pub fn clear_bit(self) -> &'a mut W {
183 self.bit(false)
184 }
185 #[doc = r"Writes raw bits to the field"]
186 #[inline(always)]
187 pub fn bit(self, value: bool) -> &'a mut W {
188 self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
189 self.w
190 }
191}
192impl R {
193 #[doc = "Bits 0:2 - Queue Number (0-2)"]
194 #[inline(always)]
195 pub fn qnb(&self) -> QNB_R {
196 QNB_R::new((self.bits & 0x07) as u8)
197 }
198 #[doc = "Bits 4:11 - Differentiated Services or Traffic Class Match"]
199 #[inline(always)]
200 pub fn dstcm(&self) -> DSTCM_R {
201 DSTCM_R::new(((self.bits >> 4) & 0xff) as u8)
202 }
203 #[doc = "Bits 12:27 - UDP Port Match"]
204 #[inline(always)]
205 pub fn udpm(&self) -> UDPM_R {
206 UDPM_R::new(((self.bits >> 12) & 0xffff) as u16)
207 }
208 #[doc = "Bit 28 - Differentiated Services or Traffic Class Match Enable"]
209 #[inline(always)]
210 pub fn dstce(&self) -> DSTCE_R {
211 DSTCE_R::new(((self.bits >> 28) & 0x01) != 0)
212 }
213 #[doc = "Bit 29 - UDP Port Match Enable"]
214 #[inline(always)]
215 pub fn udpe(&self) -> UDPE_R {
216 UDPE_R::new(((self.bits >> 29) & 0x01) != 0)
217 }
218}
219impl W {
220 #[doc = "Bits 0:2 - Queue Number (0-2)"]
221 #[inline(always)]
222 pub fn qnb(&mut self) -> QNB_W {
223 QNB_W { w: self }
224 }
225 #[doc = "Bits 4:11 - Differentiated Services or Traffic Class Match"]
226 #[inline(always)]
227 pub fn dstcm(&mut self) -> DSTCM_W {
228 DSTCM_W { w: self }
229 }
230 #[doc = "Bits 12:27 - UDP Port Match"]
231 #[inline(always)]
232 pub fn udpm(&mut self) -> UDPM_W {
233 UDPM_W { w: self }
234 }
235 #[doc = "Bit 28 - Differentiated Services or Traffic Class Match Enable"]
236 #[inline(always)]
237 pub fn dstce(&mut self) -> DSTCE_W {
238 DSTCE_W { w: self }
239 }
240 #[doc = "Bit 29 - UDP Port Match Enable"]
241 #[inline(always)]
242 pub fn udpe(&mut self) -> UDPE_W {
243 UDPE_W { w: self }
244 }
245 #[doc = "Writes raw bits to the register."]
246 #[inline(always)]
247 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
248 self.0.bits(bits);
249 self
250 }
251}
252#[doc = "Screening Type 1 Register Priority Queue (index = 0) 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gmac_st1rpq](index.html) module"]
253pub struct GMAC_ST1RPQ_SPEC;
254impl crate::RegisterSpec for GMAC_ST1RPQ_SPEC {
255 type Ux = u32;
256}
257#[doc = "`read()` method returns [gmac_st1rpq::R](R) reader structure"]
258impl crate::Readable for GMAC_ST1RPQ_SPEC {
259 type Reader = R;
260}
261#[doc = "`write(|w| ..)` method takes [gmac_st1rpq::W](W) writer structure"]
262impl crate::Writable for GMAC_ST1RPQ_SPEC {
263 type Writer = W;
264}
265#[doc = "`reset()` method sets GMAC_ST1RPQ[%s]
266to value 0"]
267impl crate::Resettable for GMAC_ST1RPQ_SPEC {
268 #[inline(always)]
269 fn reset_value() -> Self::Ux {
270 0
271 }
272}