atsamv71n21/gmac/
gmac_dcfgr.rs

1#[doc = "Register `GMAC_DCFGR` reader"]
2pub struct R(crate::R<GMAC_DCFGR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GMAC_DCFGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GMAC_DCFGR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GMAC_DCFGR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GMAC_DCFGR` writer"]
17pub struct W(crate::W<GMAC_DCFGR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GMAC_DCFGR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GMAC_DCFGR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GMAC_DCFGR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Fixed Burst Length for DMA Data Operations:\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum FBLDO_A {
41    #[doc = "1: 00001: Always use SINGLE AHB bursts"]
42    SINGLE = 1,
43    #[doc = "4: 001xx: Attempt to use INCR4 AHB bursts (Default)"]
44    INCR4 = 4,
45    #[doc = "8: 01xxx: Attempt to use INCR8 AHB bursts"]
46    INCR8 = 8,
47    #[doc = "16: 1xxxx: Attempt to use INCR16 AHB bursts"]
48    INCR16 = 16,
49}
50impl From<FBLDO_A> for u8 {
51    #[inline(always)]
52    fn from(variant: FBLDO_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `FBLDO` reader - Fixed Burst Length for DMA Data Operations:"]
57pub struct FBLDO_R(crate::FieldReader<u8, FBLDO_A>);
58impl FBLDO_R {
59    #[inline(always)]
60    pub(crate) fn new(bits: u8) -> Self {
61        FBLDO_R(crate::FieldReader::new(bits))
62    }
63    #[doc = r"Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> Option<FBLDO_A> {
66        match self.bits {
67            1 => Some(FBLDO_A::SINGLE),
68            4 => Some(FBLDO_A::INCR4),
69            8 => Some(FBLDO_A::INCR8),
70            16 => Some(FBLDO_A::INCR16),
71            _ => None,
72        }
73    }
74    #[doc = "Checks if the value of the field is `SINGLE`"]
75    #[inline(always)]
76    pub fn is_single(&self) -> bool {
77        **self == FBLDO_A::SINGLE
78    }
79    #[doc = "Checks if the value of the field is `INCR4`"]
80    #[inline(always)]
81    pub fn is_incr4(&self) -> bool {
82        **self == FBLDO_A::INCR4
83    }
84    #[doc = "Checks if the value of the field is `INCR8`"]
85    #[inline(always)]
86    pub fn is_incr8(&self) -> bool {
87        **self == FBLDO_A::INCR8
88    }
89    #[doc = "Checks if the value of the field is `INCR16`"]
90    #[inline(always)]
91    pub fn is_incr16(&self) -> bool {
92        **self == FBLDO_A::INCR16
93    }
94}
95impl core::ops::Deref for FBLDO_R {
96    type Target = crate::FieldReader<u8, FBLDO_A>;
97    #[inline(always)]
98    fn deref(&self) -> &Self::Target {
99        &self.0
100    }
101}
102#[doc = "Field `FBLDO` writer - Fixed Burst Length for DMA Data Operations:"]
103pub struct FBLDO_W<'a> {
104    w: &'a mut W,
105}
106impl<'a> FBLDO_W<'a> {
107    #[doc = r"Writes `variant` to the field"]
108    #[inline(always)]
109    pub fn variant(self, variant: FBLDO_A) -> &'a mut W {
110        unsafe { self.bits(variant.into()) }
111    }
112    #[doc = "00001: Always use SINGLE AHB bursts"]
113    #[inline(always)]
114    pub fn single(self) -> &'a mut W {
115        self.variant(FBLDO_A::SINGLE)
116    }
117    #[doc = "001xx: Attempt to use INCR4 AHB bursts (Default)"]
118    #[inline(always)]
119    pub fn incr4(self) -> &'a mut W {
120        self.variant(FBLDO_A::INCR4)
121    }
122    #[doc = "01xxx: Attempt to use INCR8 AHB bursts"]
123    #[inline(always)]
124    pub fn incr8(self) -> &'a mut W {
125        self.variant(FBLDO_A::INCR8)
126    }
127    #[doc = "1xxxx: Attempt to use INCR16 AHB bursts"]
128    #[inline(always)]
129    pub fn incr16(self) -> &'a mut W {
130        self.variant(FBLDO_A::INCR16)
131    }
132    #[doc = r"Writes raw bits to the field"]
133    #[inline(always)]
134    pub unsafe fn bits(self, value: u8) -> &'a mut W {
135        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
136        self.w
137    }
138}
139#[doc = "Field `ESMA` reader - Endian Swap Mode Enable for Management Descriptor Accesses"]
140pub struct ESMA_R(crate::FieldReader<bool, bool>);
141impl ESMA_R {
142    #[inline(always)]
143    pub(crate) fn new(bits: bool) -> Self {
144        ESMA_R(crate::FieldReader::new(bits))
145    }
146}
147impl core::ops::Deref for ESMA_R {
148    type Target = crate::FieldReader<bool, bool>;
149    #[inline(always)]
150    fn deref(&self) -> &Self::Target {
151        &self.0
152    }
153}
154#[doc = "Field `ESMA` writer - Endian Swap Mode Enable for Management Descriptor Accesses"]
155pub struct ESMA_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> ESMA_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
173        self.w
174    }
175}
176#[doc = "Field `ESPA` reader - Endian Swap Mode Enable for Packet Data Accesses"]
177pub struct ESPA_R(crate::FieldReader<bool, bool>);
178impl ESPA_R {
179    #[inline(always)]
180    pub(crate) fn new(bits: bool) -> Self {
181        ESPA_R(crate::FieldReader::new(bits))
182    }
183}
184impl core::ops::Deref for ESPA_R {
185    type Target = crate::FieldReader<bool, bool>;
186    #[inline(always)]
187    fn deref(&self) -> &Self::Target {
188        &self.0
189    }
190}
191#[doc = "Field `ESPA` writer - Endian Swap Mode Enable for Packet Data Accesses"]
192pub struct ESPA_W<'a> {
193    w: &'a mut W,
194}
195impl<'a> ESPA_W<'a> {
196    #[doc = r"Sets the field bit"]
197    #[inline(always)]
198    pub fn set_bit(self) -> &'a mut W {
199        self.bit(true)
200    }
201    #[doc = r"Clears the field bit"]
202    #[inline(always)]
203    pub fn clear_bit(self) -> &'a mut W {
204        self.bit(false)
205    }
206    #[doc = r"Writes raw bits to the field"]
207    #[inline(always)]
208    pub fn bit(self, value: bool) -> &'a mut W {
209        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
210        self.w
211    }
212}
213#[doc = "Receiver Packet Buffer Memory Size Select\n\nValue on reset: 0"]
214#[derive(Clone, Copy, Debug, PartialEq)]
215#[repr(u8)]
216pub enum RXBMS_A {
217    #[doc = "0: 4/8 Kbyte Memory Size"]
218    EIGHTH = 0,
219    #[doc = "1: 4/4 Kbytes Memory Size"]
220    QUARTER = 1,
221    #[doc = "2: 4/2 Kbytes Memory Size"]
222    HALF = 2,
223    #[doc = "3: 4 Kbytes Memory Size"]
224    FULL = 3,
225}
226impl From<RXBMS_A> for u8 {
227    #[inline(always)]
228    fn from(variant: RXBMS_A) -> Self {
229        variant as _
230    }
231}
232#[doc = "Field `RXBMS` reader - Receiver Packet Buffer Memory Size Select"]
233pub struct RXBMS_R(crate::FieldReader<u8, RXBMS_A>);
234impl RXBMS_R {
235    #[inline(always)]
236    pub(crate) fn new(bits: u8) -> Self {
237        RXBMS_R(crate::FieldReader::new(bits))
238    }
239    #[doc = r"Get enumerated values variant"]
240    #[inline(always)]
241    pub fn variant(&self) -> RXBMS_A {
242        match self.bits {
243            0 => RXBMS_A::EIGHTH,
244            1 => RXBMS_A::QUARTER,
245            2 => RXBMS_A::HALF,
246            3 => RXBMS_A::FULL,
247            _ => unreachable!(),
248        }
249    }
250    #[doc = "Checks if the value of the field is `EIGHTH`"]
251    #[inline(always)]
252    pub fn is_eighth(&self) -> bool {
253        **self == RXBMS_A::EIGHTH
254    }
255    #[doc = "Checks if the value of the field is `QUARTER`"]
256    #[inline(always)]
257    pub fn is_quarter(&self) -> bool {
258        **self == RXBMS_A::QUARTER
259    }
260    #[doc = "Checks if the value of the field is `HALF`"]
261    #[inline(always)]
262    pub fn is_half(&self) -> bool {
263        **self == RXBMS_A::HALF
264    }
265    #[doc = "Checks if the value of the field is `FULL`"]
266    #[inline(always)]
267    pub fn is_full(&self) -> bool {
268        **self == RXBMS_A::FULL
269    }
270}
271impl core::ops::Deref for RXBMS_R {
272    type Target = crate::FieldReader<u8, RXBMS_A>;
273    #[inline(always)]
274    fn deref(&self) -> &Self::Target {
275        &self.0
276    }
277}
278#[doc = "Field `RXBMS` writer - Receiver Packet Buffer Memory Size Select"]
279pub struct RXBMS_W<'a> {
280    w: &'a mut W,
281}
282impl<'a> RXBMS_W<'a> {
283    #[doc = r"Writes `variant` to the field"]
284    #[inline(always)]
285    pub fn variant(self, variant: RXBMS_A) -> &'a mut W {
286        self.bits(variant.into())
287    }
288    #[doc = "4/8 Kbyte Memory Size"]
289    #[inline(always)]
290    pub fn eighth(self) -> &'a mut W {
291        self.variant(RXBMS_A::EIGHTH)
292    }
293    #[doc = "4/4 Kbytes Memory Size"]
294    #[inline(always)]
295    pub fn quarter(self) -> &'a mut W {
296        self.variant(RXBMS_A::QUARTER)
297    }
298    #[doc = "4/2 Kbytes Memory Size"]
299    #[inline(always)]
300    pub fn half(self) -> &'a mut W {
301        self.variant(RXBMS_A::HALF)
302    }
303    #[doc = "4 Kbytes Memory Size"]
304    #[inline(always)]
305    pub fn full(self) -> &'a mut W {
306        self.variant(RXBMS_A::FULL)
307    }
308    #[doc = r"Writes raw bits to the field"]
309    #[inline(always)]
310    pub fn bits(self, value: u8) -> &'a mut W {
311        self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
312        self.w
313    }
314}
315#[doc = "Field `TXPBMS` reader - Transmitter Packet Buffer Memory Size Select"]
316pub struct TXPBMS_R(crate::FieldReader<bool, bool>);
317impl TXPBMS_R {
318    #[inline(always)]
319    pub(crate) fn new(bits: bool) -> Self {
320        TXPBMS_R(crate::FieldReader::new(bits))
321    }
322}
323impl core::ops::Deref for TXPBMS_R {
324    type Target = crate::FieldReader<bool, bool>;
325    #[inline(always)]
326    fn deref(&self) -> &Self::Target {
327        &self.0
328    }
329}
330#[doc = "Field `TXPBMS` writer - Transmitter Packet Buffer Memory Size Select"]
331pub struct TXPBMS_W<'a> {
332    w: &'a mut W,
333}
334impl<'a> TXPBMS_W<'a> {
335    #[doc = r"Sets the field bit"]
336    #[inline(always)]
337    pub fn set_bit(self) -> &'a mut W {
338        self.bit(true)
339    }
340    #[doc = r"Clears the field bit"]
341    #[inline(always)]
342    pub fn clear_bit(self) -> &'a mut W {
343        self.bit(false)
344    }
345    #[doc = r"Writes raw bits to the field"]
346    #[inline(always)]
347    pub fn bit(self, value: bool) -> &'a mut W {
348        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
349        self.w
350    }
351}
352#[doc = "Field `TXCOEN` reader - Transmitter Checksum Generation Offload Enable"]
353pub struct TXCOEN_R(crate::FieldReader<bool, bool>);
354impl TXCOEN_R {
355    #[inline(always)]
356    pub(crate) fn new(bits: bool) -> Self {
357        TXCOEN_R(crate::FieldReader::new(bits))
358    }
359}
360impl core::ops::Deref for TXCOEN_R {
361    type Target = crate::FieldReader<bool, bool>;
362    #[inline(always)]
363    fn deref(&self) -> &Self::Target {
364        &self.0
365    }
366}
367#[doc = "Field `TXCOEN` writer - Transmitter Checksum Generation Offload Enable"]
368pub struct TXCOEN_W<'a> {
369    w: &'a mut W,
370}
371impl<'a> TXCOEN_W<'a> {
372    #[doc = r"Sets the field bit"]
373    #[inline(always)]
374    pub fn set_bit(self) -> &'a mut W {
375        self.bit(true)
376    }
377    #[doc = r"Clears the field bit"]
378    #[inline(always)]
379    pub fn clear_bit(self) -> &'a mut W {
380        self.bit(false)
381    }
382    #[doc = r"Writes raw bits to the field"]
383    #[inline(always)]
384    pub fn bit(self, value: bool) -> &'a mut W {
385        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
386        self.w
387    }
388}
389#[doc = "Field `DRBS` reader - DMA Receive Buffer Size"]
390pub struct DRBS_R(crate::FieldReader<u8, u8>);
391impl DRBS_R {
392    #[inline(always)]
393    pub(crate) fn new(bits: u8) -> Self {
394        DRBS_R(crate::FieldReader::new(bits))
395    }
396}
397impl core::ops::Deref for DRBS_R {
398    type Target = crate::FieldReader<u8, u8>;
399    #[inline(always)]
400    fn deref(&self) -> &Self::Target {
401        &self.0
402    }
403}
404#[doc = "Field `DRBS` writer - DMA Receive Buffer Size"]
405pub struct DRBS_W<'a> {
406    w: &'a mut W,
407}
408impl<'a> DRBS_W<'a> {
409    #[doc = r"Writes raw bits to the field"]
410    #[inline(always)]
411    pub unsafe fn bits(self, value: u8) -> &'a mut W {
412        self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16);
413        self.w
414    }
415}
416#[doc = "Field `DDRP` reader - DMA Discard Receive Packets"]
417pub struct DDRP_R(crate::FieldReader<bool, bool>);
418impl DDRP_R {
419    #[inline(always)]
420    pub(crate) fn new(bits: bool) -> Self {
421        DDRP_R(crate::FieldReader::new(bits))
422    }
423}
424impl core::ops::Deref for DDRP_R {
425    type Target = crate::FieldReader<bool, bool>;
426    #[inline(always)]
427    fn deref(&self) -> &Self::Target {
428        &self.0
429    }
430}
431#[doc = "Field `DDRP` writer - DMA Discard Receive Packets"]
432pub struct DDRP_W<'a> {
433    w: &'a mut W,
434}
435impl<'a> DDRP_W<'a> {
436    #[doc = r"Sets the field bit"]
437    #[inline(always)]
438    pub fn set_bit(self) -> &'a mut W {
439        self.bit(true)
440    }
441    #[doc = r"Clears the field bit"]
442    #[inline(always)]
443    pub fn clear_bit(self) -> &'a mut W {
444        self.bit(false)
445    }
446    #[doc = r"Writes raw bits to the field"]
447    #[inline(always)]
448    pub fn bit(self, value: bool) -> &'a mut W {
449        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
450        self.w
451    }
452}
453impl R {
454    #[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"]
455    #[inline(always)]
456    pub fn fbldo(&self) -> FBLDO_R {
457        FBLDO_R::new((self.bits & 0x1f) as u8)
458    }
459    #[doc = "Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses"]
460    #[inline(always)]
461    pub fn esma(&self) -> ESMA_R {
462        ESMA_R::new(((self.bits >> 6) & 0x01) != 0)
463    }
464    #[doc = "Bit 7 - Endian Swap Mode Enable for Packet Data Accesses"]
465    #[inline(always)]
466    pub fn espa(&self) -> ESPA_R {
467        ESPA_R::new(((self.bits >> 7) & 0x01) != 0)
468    }
469    #[doc = "Bits 8:9 - Receiver Packet Buffer Memory Size Select"]
470    #[inline(always)]
471    pub fn rxbms(&self) -> RXBMS_R {
472        RXBMS_R::new(((self.bits >> 8) & 0x03) as u8)
473    }
474    #[doc = "Bit 10 - Transmitter Packet Buffer Memory Size Select"]
475    #[inline(always)]
476    pub fn txpbms(&self) -> TXPBMS_R {
477        TXPBMS_R::new(((self.bits >> 10) & 0x01) != 0)
478    }
479    #[doc = "Bit 11 - Transmitter Checksum Generation Offload Enable"]
480    #[inline(always)]
481    pub fn txcoen(&self) -> TXCOEN_R {
482        TXCOEN_R::new(((self.bits >> 11) & 0x01) != 0)
483    }
484    #[doc = "Bits 16:23 - DMA Receive Buffer Size"]
485    #[inline(always)]
486    pub fn drbs(&self) -> DRBS_R {
487        DRBS_R::new(((self.bits >> 16) & 0xff) as u8)
488    }
489    #[doc = "Bit 24 - DMA Discard Receive Packets"]
490    #[inline(always)]
491    pub fn ddrp(&self) -> DDRP_R {
492        DDRP_R::new(((self.bits >> 24) & 0x01) != 0)
493    }
494}
495impl W {
496    #[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"]
497    #[inline(always)]
498    pub fn fbldo(&mut self) -> FBLDO_W {
499        FBLDO_W { w: self }
500    }
501    #[doc = "Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses"]
502    #[inline(always)]
503    pub fn esma(&mut self) -> ESMA_W {
504        ESMA_W { w: self }
505    }
506    #[doc = "Bit 7 - Endian Swap Mode Enable for Packet Data Accesses"]
507    #[inline(always)]
508    pub fn espa(&mut self) -> ESPA_W {
509        ESPA_W { w: self }
510    }
511    #[doc = "Bits 8:9 - Receiver Packet Buffer Memory Size Select"]
512    #[inline(always)]
513    pub fn rxbms(&mut self) -> RXBMS_W {
514        RXBMS_W { w: self }
515    }
516    #[doc = "Bit 10 - Transmitter Packet Buffer Memory Size Select"]
517    #[inline(always)]
518    pub fn txpbms(&mut self) -> TXPBMS_W {
519        TXPBMS_W { w: self }
520    }
521    #[doc = "Bit 11 - Transmitter Checksum Generation Offload Enable"]
522    #[inline(always)]
523    pub fn txcoen(&mut self) -> TXCOEN_W {
524        TXCOEN_W { w: self }
525    }
526    #[doc = "Bits 16:23 - DMA Receive Buffer Size"]
527    #[inline(always)]
528    pub fn drbs(&mut self) -> DRBS_W {
529        DRBS_W { w: self }
530    }
531    #[doc = "Bit 24 - DMA Discard Receive Packets"]
532    #[inline(always)]
533    pub fn ddrp(&mut self) -> DDRP_W {
534        DDRP_W { w: self }
535    }
536    #[doc = "Writes raw bits to the register."]
537    #[inline(always)]
538    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
539        self.0.bits(bits);
540        self
541    }
542}
543#[doc = "DMA Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gmac_dcfgr](index.html) module"]
544pub struct GMAC_DCFGR_SPEC;
545impl crate::RegisterSpec for GMAC_DCFGR_SPEC {
546    type Ux = u32;
547}
548#[doc = "`read()` method returns [gmac_dcfgr::R](R) reader structure"]
549impl crate::Readable for GMAC_DCFGR_SPEC {
550    type Reader = R;
551}
552#[doc = "`write(|w| ..)` method takes [gmac_dcfgr::W](W) writer structure"]
553impl crate::Writable for GMAC_DCFGR_SPEC {
554    type Writer = W;
555}
556#[doc = "`reset()` method sets GMAC_DCFGR to value 0"]
557impl crate::Resettable for GMAC_DCFGR_SPEC {
558    #[inline(always)]
559    fn reset_value() -> Self::Ux {
560        0
561    }
562}
atsamv71n21/gmac/gmac_dcfgr.rs

atsamv71n21/gmac/
gmac_dcfgr.rs
