atsamv71n21/twihs0/
twihs_ier.rs

1#[doc = "Register `TWIHS_IER` writer"]
2pub struct W(crate::W<TWIHS_IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<TWIHS_IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<TWIHS_IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<TWIHS_IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `TXCOMP` writer - Transmission Completed Interrupt Enable"]
23pub struct TXCOMP_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> TXCOMP_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `RXRDY` writer - Receive Holding Register Ready Interrupt Enable"]
45pub struct RXRDY_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> RXRDY_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63        self.w
64    }
65}
66#[doc = "Field `TXRDY` writer - Transmit Holding Register Ready Interrupt Enable"]
67pub struct TXRDY_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> TXRDY_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
85        self.w
86    }
87}
88#[doc = "Field `SVACC` writer - Slave Access Interrupt Enable"]
89pub struct SVACC_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> SVACC_W<'a> {
93    #[doc = r"Sets the field bit"]
94    #[inline(always)]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r"Clears the field bit"]
99    #[inline(always)]
100    pub fn clear_bit(self) -> &'a mut W {
101        self.bit(false)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub fn bit(self, value: bool) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
107        self.w
108    }
109}
110#[doc = "Field `GACC` writer - General Call Access Interrupt Enable"]
111pub struct GACC_W<'a> {
112    w: &'a mut W,
113}
114impl<'a> GACC_W<'a> {
115    #[doc = r"Sets the field bit"]
116    #[inline(always)]
117    pub fn set_bit(self) -> &'a mut W {
118        self.bit(true)
119    }
120    #[doc = r"Clears the field bit"]
121    #[inline(always)]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r"Writes raw bits to the field"]
126    #[inline(always)]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
129        self.w
130    }
131}
132#[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"]
133pub struct OVRE_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> OVRE_W<'a> {
137    #[doc = r"Sets the field bit"]
138    #[inline(always)]
139    pub fn set_bit(self) -> &'a mut W {
140        self.bit(true)
141    }
142    #[doc = r"Clears the field bit"]
143    #[inline(always)]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r"Writes raw bits to the field"]
148    #[inline(always)]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
151        self.w
152    }
153}
154#[doc = "Field `UNRE` writer - Underrun Error Interrupt Enable"]
155pub struct UNRE_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> UNRE_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
173        self.w
174    }
175}
176#[doc = "Field `NACK` writer - Not Acknowledge Interrupt Enable"]
177pub struct NACK_W<'a> {
178    w: &'a mut W,
179}
180impl<'a> NACK_W<'a> {
181    #[doc = r"Sets the field bit"]
182    #[inline(always)]
183    pub fn set_bit(self) -> &'a mut W {
184        self.bit(true)
185    }
186    #[doc = r"Clears the field bit"]
187    #[inline(always)]
188    pub fn clear_bit(self) -> &'a mut W {
189        self.bit(false)
190    }
191    #[doc = r"Writes raw bits to the field"]
192    #[inline(always)]
193    pub fn bit(self, value: bool) -> &'a mut W {
194        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
195        self.w
196    }
197}
198#[doc = "Field `ARBLST` writer - Arbitration Lost Interrupt Enable"]
199pub struct ARBLST_W<'a> {
200    w: &'a mut W,
201}
202impl<'a> ARBLST_W<'a> {
203    #[doc = r"Sets the field bit"]
204    #[inline(always)]
205    pub fn set_bit(self) -> &'a mut W {
206        self.bit(true)
207    }
208    #[doc = r"Clears the field bit"]
209    #[inline(always)]
210    pub fn clear_bit(self) -> &'a mut W {
211        self.bit(false)
212    }
213    #[doc = r"Writes raw bits to the field"]
214    #[inline(always)]
215    pub fn bit(self, value: bool) -> &'a mut W {
216        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
217        self.w
218    }
219}
220#[doc = "Field `SCL_WS` writer - Clock Wait State Interrupt Enable"]
221pub struct SCL_WS_W<'a> {
222    w: &'a mut W,
223}
224impl<'a> SCL_WS_W<'a> {
225    #[doc = r"Sets the field bit"]
226    #[inline(always)]
227    pub fn set_bit(self) -> &'a mut W {
228        self.bit(true)
229    }
230    #[doc = r"Clears the field bit"]
231    #[inline(always)]
232    pub fn clear_bit(self) -> &'a mut W {
233        self.bit(false)
234    }
235    #[doc = r"Writes raw bits to the field"]
236    #[inline(always)]
237    pub fn bit(self, value: bool) -> &'a mut W {
238        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
239        self.w
240    }
241}
242#[doc = "Field `EOSACC` writer - End Of Slave Access Interrupt Enable"]
243pub struct EOSACC_W<'a> {
244    w: &'a mut W,
245}
246impl<'a> EOSACC_W<'a> {
247    #[doc = r"Sets the field bit"]
248    #[inline(always)]
249    pub fn set_bit(self) -> &'a mut W {
250        self.bit(true)
251    }
252    #[doc = r"Clears the field bit"]
253    #[inline(always)]
254    pub fn clear_bit(self) -> &'a mut W {
255        self.bit(false)
256    }
257    #[doc = r"Writes raw bits to the field"]
258    #[inline(always)]
259    pub fn bit(self, value: bool) -> &'a mut W {
260        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
261        self.w
262    }
263}
264#[doc = "Field `MCACK` writer - Master Code Acknowledge Interrupt Enable"]
265pub struct MCACK_W<'a> {
266    w: &'a mut W,
267}
268impl<'a> MCACK_W<'a> {
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
283        self.w
284    }
285}
286#[doc = "Field `TOUT` writer - Timeout Error Interrupt Enable"]
287pub struct TOUT_W<'a> {
288    w: &'a mut W,
289}
290impl<'a> TOUT_W<'a> {
291    #[doc = r"Sets the field bit"]
292    #[inline(always)]
293    pub fn set_bit(self) -> &'a mut W {
294        self.bit(true)
295    }
296    #[doc = r"Clears the field bit"]
297    #[inline(always)]
298    pub fn clear_bit(self) -> &'a mut W {
299        self.bit(false)
300    }
301    #[doc = r"Writes raw bits to the field"]
302    #[inline(always)]
303    pub fn bit(self, value: bool) -> &'a mut W {
304        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
305        self.w
306    }
307}
308#[doc = "Field `PECERR` writer - PEC Error Interrupt Enable"]
309pub struct PECERR_W<'a> {
310    w: &'a mut W,
311}
312impl<'a> PECERR_W<'a> {
313    #[doc = r"Sets the field bit"]
314    #[inline(always)]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r"Clears the field bit"]
319    #[inline(always)]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r"Writes raw bits to the field"]
324    #[inline(always)]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
327        self.w
328    }
329}
330#[doc = "Field `SMBDAM` writer - SMBus Default Address Match Interrupt Enable"]
331pub struct SMBDAM_W<'a> {
332    w: &'a mut W,
333}
334impl<'a> SMBDAM_W<'a> {
335    #[doc = r"Sets the field bit"]
336    #[inline(always)]
337    pub fn set_bit(self) -> &'a mut W {
338        self.bit(true)
339    }
340    #[doc = r"Clears the field bit"]
341    #[inline(always)]
342    pub fn clear_bit(self) -> &'a mut W {
343        self.bit(false)
344    }
345    #[doc = r"Writes raw bits to the field"]
346    #[inline(always)]
347    pub fn bit(self, value: bool) -> &'a mut W {
348        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
349        self.w
350    }
351}
352#[doc = "Field `SMBHHM` writer - SMBus Host Header Address Match Interrupt Enable"]
353pub struct SMBHHM_W<'a> {
354    w: &'a mut W,
355}
356impl<'a> SMBHHM_W<'a> {
357    #[doc = r"Sets the field bit"]
358    #[inline(always)]
359    pub fn set_bit(self) -> &'a mut W {
360        self.bit(true)
361    }
362    #[doc = r"Clears the field bit"]
363    #[inline(always)]
364    pub fn clear_bit(self) -> &'a mut W {
365        self.bit(false)
366    }
367    #[doc = r"Writes raw bits to the field"]
368    #[inline(always)]
369    pub fn bit(self, value: bool) -> &'a mut W {
370        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
371        self.w
372    }
373}
374impl W {
375    #[doc = "Bit 0 - Transmission Completed Interrupt Enable"]
376    #[inline(always)]
377    pub fn txcomp(&mut self) -> TXCOMP_W {
378        TXCOMP_W { w: self }
379    }
380    #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Enable"]
381    #[inline(always)]
382    pub fn rxrdy(&mut self) -> RXRDY_W {
383        RXRDY_W { w: self }
384    }
385    #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Enable"]
386    #[inline(always)]
387    pub fn txrdy(&mut self) -> TXRDY_W {
388        TXRDY_W { w: self }
389    }
390    #[doc = "Bit 4 - Slave Access Interrupt Enable"]
391    #[inline(always)]
392    pub fn svacc(&mut self) -> SVACC_W {
393        SVACC_W { w: self }
394    }
395    #[doc = "Bit 5 - General Call Access Interrupt Enable"]
396    #[inline(always)]
397    pub fn gacc(&mut self) -> GACC_W {
398        GACC_W { w: self }
399    }
400    #[doc = "Bit 6 - Overrun Error Interrupt Enable"]
401    #[inline(always)]
402    pub fn ovre(&mut self) -> OVRE_W {
403        OVRE_W { w: self }
404    }
405    #[doc = "Bit 7 - Underrun Error Interrupt Enable"]
406    #[inline(always)]
407    pub fn unre(&mut self) -> UNRE_W {
408        UNRE_W { w: self }
409    }
410    #[doc = "Bit 8 - Not Acknowledge Interrupt Enable"]
411    #[inline(always)]
412    pub fn nack(&mut self) -> NACK_W {
413        NACK_W { w: self }
414    }
415    #[doc = "Bit 9 - Arbitration Lost Interrupt Enable"]
416    #[inline(always)]
417    pub fn arblst(&mut self) -> ARBLST_W {
418        ARBLST_W { w: self }
419    }
420    #[doc = "Bit 10 - Clock Wait State Interrupt Enable"]
421    #[inline(always)]
422    pub fn scl_ws(&mut self) -> SCL_WS_W {
423        SCL_WS_W { w: self }
424    }
425    #[doc = "Bit 11 - End Of Slave Access Interrupt Enable"]
426    #[inline(always)]
427    pub fn eosacc(&mut self) -> EOSACC_W {
428        EOSACC_W { w: self }
429    }
430    #[doc = "Bit 16 - Master Code Acknowledge Interrupt Enable"]
431    #[inline(always)]
432    pub fn mcack(&mut self) -> MCACK_W {
433        MCACK_W { w: self }
434    }
435    #[doc = "Bit 18 - Timeout Error Interrupt Enable"]
436    #[inline(always)]
437    pub fn tout(&mut self) -> TOUT_W {
438        TOUT_W { w: self }
439    }
440    #[doc = "Bit 19 - PEC Error Interrupt Enable"]
441    #[inline(always)]
442    pub fn pecerr(&mut self) -> PECERR_W {
443        PECERR_W { w: self }
444    }
445    #[doc = "Bit 20 - SMBus Default Address Match Interrupt Enable"]
446    #[inline(always)]
447    pub fn smbdam(&mut self) -> SMBDAM_W {
448        SMBDAM_W { w: self }
449    }
450    #[doc = "Bit 21 - SMBus Host Header Address Match Interrupt Enable"]
451    #[inline(always)]
452    pub fn smbhhm(&mut self) -> SMBHHM_W {
453        SMBHHM_W { w: self }
454    }
455    #[doc = "Writes raw bits to the register."]
456    #[inline(always)]
457    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
458        self.0.bits(bits);
459        self
460    }
461}
462#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [twihs_ier](index.html) module"]
463pub struct TWIHS_IER_SPEC;
464impl crate::RegisterSpec for TWIHS_IER_SPEC {
465    type Ux = u32;
466}
467#[doc = "`write(|w| ..)` method takes [twihs_ier::W](W) writer structure"]
468impl crate::Writable for TWIHS_IER_SPEC {
469    type Writer = W;
470}
471#[doc = "`reset()` method sets TWIHS_IER to value 0"]
472impl crate::Resettable for TWIHS_IER_SPEC {
473    #[inline(always)]
474    fn reset_value() -> Self::Ux {
475        0
476    }
477}
atsamv71n21/twihs0/twihs_ier.rs

atsamv71n21/twihs0/
twihs_ier.rs
