atsamv70j19/rtc/
rtc_ier.rs1#[doc = "Register `RTC_IER` writer"]
2pub struct W(crate::W<RTC_IER_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<RTC_IER_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<RTC_IER_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<RTC_IER_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `ACKEN` writer - Acknowledge Update Interrupt Enable"]
23pub struct ACKEN_W<'a> {
24 w: &'a mut W,
25}
26impl<'a> ACKEN_W<'a> {
27 #[doc = r"Sets the field bit"]
28 #[inline(always)]
29 pub fn set_bit(self) -> &'a mut W {
30 self.bit(true)
31 }
32 #[doc = r"Clears the field bit"]
33 #[inline(always)]
34 pub fn clear_bit(self) -> &'a mut W {
35 self.bit(false)
36 }
37 #[doc = r"Writes raw bits to the field"]
38 #[inline(always)]
39 pub fn bit(self, value: bool) -> &'a mut W {
40 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41 self.w
42 }
43}
44#[doc = "Field `ALREN` writer - Alarm Interrupt Enable"]
45pub struct ALREN_W<'a> {
46 w: &'a mut W,
47}
48impl<'a> ALREN_W<'a> {
49 #[doc = r"Sets the field bit"]
50 #[inline(always)]
51 pub fn set_bit(self) -> &'a mut W {
52 self.bit(true)
53 }
54 #[doc = r"Clears the field bit"]
55 #[inline(always)]
56 pub fn clear_bit(self) -> &'a mut W {
57 self.bit(false)
58 }
59 #[doc = r"Writes raw bits to the field"]
60 #[inline(always)]
61 pub fn bit(self, value: bool) -> &'a mut W {
62 self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63 self.w
64 }
65}
66#[doc = "Field `SECEN` writer - Second Event Interrupt Enable"]
67pub struct SECEN_W<'a> {
68 w: &'a mut W,
69}
70impl<'a> SECEN_W<'a> {
71 #[doc = r"Sets the field bit"]
72 #[inline(always)]
73 pub fn set_bit(self) -> &'a mut W {
74 self.bit(true)
75 }
76 #[doc = r"Clears the field bit"]
77 #[inline(always)]
78 pub fn clear_bit(self) -> &'a mut W {
79 self.bit(false)
80 }
81 #[doc = r"Writes raw bits to the field"]
82 #[inline(always)]
83 pub fn bit(self, value: bool) -> &'a mut W {
84 self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
85 self.w
86 }
87}
88#[doc = "Field `TIMEN` writer - Time Event Interrupt Enable"]
89pub struct TIMEN_W<'a> {
90 w: &'a mut W,
91}
92impl<'a> TIMEN_W<'a> {
93 #[doc = r"Sets the field bit"]
94 #[inline(always)]
95 pub fn set_bit(self) -> &'a mut W {
96 self.bit(true)
97 }
98 #[doc = r"Clears the field bit"]
99 #[inline(always)]
100 pub fn clear_bit(self) -> &'a mut W {
101 self.bit(false)
102 }
103 #[doc = r"Writes raw bits to the field"]
104 #[inline(always)]
105 pub fn bit(self, value: bool) -> &'a mut W {
106 self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
107 self.w
108 }
109}
110#[doc = "Field `CALEN` writer - Calendar Event Interrupt Enable"]
111pub struct CALEN_W<'a> {
112 w: &'a mut W,
113}
114impl<'a> CALEN_W<'a> {
115 #[doc = r"Sets the field bit"]
116 #[inline(always)]
117 pub fn set_bit(self) -> &'a mut W {
118 self.bit(true)
119 }
120 #[doc = r"Clears the field bit"]
121 #[inline(always)]
122 pub fn clear_bit(self) -> &'a mut W {
123 self.bit(false)
124 }
125 #[doc = r"Writes raw bits to the field"]
126 #[inline(always)]
127 pub fn bit(self, value: bool) -> &'a mut W {
128 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
129 self.w
130 }
131}
132#[doc = "Field `TDERREN` writer - Time and/or Date Error Interrupt Enable"]
133pub struct TDERREN_W<'a> {
134 w: &'a mut W,
135}
136impl<'a> TDERREN_W<'a> {
137 #[doc = r"Sets the field bit"]
138 #[inline(always)]
139 pub fn set_bit(self) -> &'a mut W {
140 self.bit(true)
141 }
142 #[doc = r"Clears the field bit"]
143 #[inline(always)]
144 pub fn clear_bit(self) -> &'a mut W {
145 self.bit(false)
146 }
147 #[doc = r"Writes raw bits to the field"]
148 #[inline(always)]
149 pub fn bit(self, value: bool) -> &'a mut W {
150 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
151 self.w
152 }
153}
154impl W {
155 #[doc = "Bit 0 - Acknowledge Update Interrupt Enable"]
156 #[inline(always)]
157 pub fn acken(&mut self) -> ACKEN_W {
158 ACKEN_W { w: self }
159 }
160 #[doc = "Bit 1 - Alarm Interrupt Enable"]
161 #[inline(always)]
162 pub fn alren(&mut self) -> ALREN_W {
163 ALREN_W { w: self }
164 }
165 #[doc = "Bit 2 - Second Event Interrupt Enable"]
166 #[inline(always)]
167 pub fn secen(&mut self) -> SECEN_W {
168 SECEN_W { w: self }
169 }
170 #[doc = "Bit 3 - Time Event Interrupt Enable"]
171 #[inline(always)]
172 pub fn timen(&mut self) -> TIMEN_W {
173 TIMEN_W { w: self }
174 }
175 #[doc = "Bit 4 - Calendar Event Interrupt Enable"]
176 #[inline(always)]
177 pub fn calen(&mut self) -> CALEN_W {
178 CALEN_W { w: self }
179 }
180 #[doc = "Bit 5 - Time and/or Date Error Interrupt Enable"]
181 #[inline(always)]
182 pub fn tderren(&mut self) -> TDERREN_W {
183 TDERREN_W { w: self }
184 }
185 #[doc = "Writes raw bits to the register."]
186 #[inline(always)]
187 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
188 self.0.bits(bits);
189 self
190 }
191}
192#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtc_ier](index.html) module"]
193pub struct RTC_IER_SPEC;
194impl crate::RegisterSpec for RTC_IER_SPEC {
195 type Ux = u32;
196}
197#[doc = "`write(|w| ..)` method takes [rtc_ier::W](W) writer structure"]
198impl crate::Writable for RTC_IER_SPEC {
199 type Writer = W;
200}
201#[doc = "`reset()` method sets RTC_IER to value 0"]
202impl crate::Resettable for RTC_IER_SPEC {
203 #[inline(always)]
204 fn reset_value() -> Self::Ux {
205 0
206 }
207}