atsams70q21/pwm0/
pwm_cmupd0.rs

1#[doc = "Register `PWM_CMUPD0` writer"]
2pub struct W(crate::W<PWM_CMUPD0_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<PWM_CMUPD0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<PWM_CMUPD0_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<PWM_CMUPD0_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CPOLUP` writer - Channel Polarity Update"]
23pub struct CPOLUP_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> CPOLUP_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
41        self.w
42    }
43}
44#[doc = "Field `CPOLINVUP` writer - Channel Polarity Inversion Update"]
45pub struct CPOLINVUP_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> CPOLINVUP_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
63        self.w
64    }
65}
66impl W {
67    #[doc = "Bit 9 - Channel Polarity Update"]
68    #[inline(always)]
69    pub fn cpolup(&mut self) -> CPOLUP_W {
70        CPOLUP_W { w: self }
71    }
72    #[doc = "Bit 13 - Channel Polarity Inversion Update"]
73    #[inline(always)]
74    pub fn cpolinvup(&mut self) -> CPOLINVUP_W {
75        CPOLINVUP_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "PWM Channel Mode Update Register (ch_num = 0)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwm_cmupd0](index.html) module"]
85pub struct PWM_CMUPD0_SPEC;
86impl crate::RegisterSpec for PWM_CMUPD0_SPEC {
87    type Ux = u32;
88}
89#[doc = "`write(|w| ..)` method takes [pwm_cmupd0::W](W) writer structure"]
90impl crate::Writable for PWM_CMUPD0_SPEC {
91    type Writer = W;
92}
93#[doc = "`reset()` method sets PWM_CMUPD0 to value 0"]
94impl crate::Resettable for PWM_CMUPD0_SPEC {
95    #[inline(always)]
96    fn reset_value() -> Self::Ux {
97        0
98    }
99}
atsams70q21/pwm0/pwm_cmupd0.rs

atsams70q21/pwm0/
pwm_cmupd0.rs
