atsams70q21/spi0/
spi_cr.rs

1#[doc = "Register `SPI_CR` writer"]
2pub struct W(crate::W<SPI_CR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<SPI_CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<SPI_CR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<SPI_CR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `SPIEN` writer - SPI Enable"]
23pub struct SPIEN_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> SPIEN_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `SPIDIS` writer - SPI Disable"]
45pub struct SPIDIS_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> SPIDIS_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63        self.w
64    }
65}
66#[doc = "Field `SWRST` writer - SPI Software Reset"]
67pub struct SWRST_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> SWRST_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
85        self.w
86    }
87}
88#[doc = "Field `LASTXFER` writer - Last Transfer"]
89pub struct LASTXFER_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> LASTXFER_W<'a> {
93    #[doc = r"Sets the field bit"]
94    #[inline(always)]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r"Clears the field bit"]
99    #[inline(always)]
100    pub fn clear_bit(self) -> &'a mut W {
101        self.bit(false)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub fn bit(self, value: bool) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
107        self.w
108    }
109}
110#[doc = "Field `REQCLR` writer - Request to Clear the Comparison Trigger"]
111pub struct REQCLR_W<'a> {
112    w: &'a mut W,
113}
114impl<'a> REQCLR_W<'a> {
115    #[doc = r"Sets the field bit"]
116    #[inline(always)]
117    pub fn set_bit(self) -> &'a mut W {
118        self.bit(true)
119    }
120    #[doc = r"Clears the field bit"]
121    #[inline(always)]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r"Writes raw bits to the field"]
126    #[inline(always)]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
129        self.w
130    }
131}
132#[doc = "Field `TXFCLR` writer - Transmit FIFO Clear"]
133pub struct TXFCLR_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> TXFCLR_W<'a> {
137    #[doc = r"Sets the field bit"]
138    #[inline(always)]
139    pub fn set_bit(self) -> &'a mut W {
140        self.bit(true)
141    }
142    #[doc = r"Clears the field bit"]
143    #[inline(always)]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r"Writes raw bits to the field"]
148    #[inline(always)]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
151        self.w
152    }
153}
154#[doc = "Field `RXFCLR` writer - Receive FIFO Clear"]
155pub struct RXFCLR_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> RXFCLR_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
173        self.w
174    }
175}
176#[doc = "Field `FIFOEN` writer - FIFO Enable"]
177pub struct FIFOEN_W<'a> {
178    w: &'a mut W,
179}
180impl<'a> FIFOEN_W<'a> {
181    #[doc = r"Sets the field bit"]
182    #[inline(always)]
183    pub fn set_bit(self) -> &'a mut W {
184        self.bit(true)
185    }
186    #[doc = r"Clears the field bit"]
187    #[inline(always)]
188    pub fn clear_bit(self) -> &'a mut W {
189        self.bit(false)
190    }
191    #[doc = r"Writes raw bits to the field"]
192    #[inline(always)]
193    pub fn bit(self, value: bool) -> &'a mut W {
194        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
195        self.w
196    }
197}
198#[doc = "Field `FIFODIS` writer - FIFO Disable"]
199pub struct FIFODIS_W<'a> {
200    w: &'a mut W,
201}
202impl<'a> FIFODIS_W<'a> {
203    #[doc = r"Sets the field bit"]
204    #[inline(always)]
205    pub fn set_bit(self) -> &'a mut W {
206        self.bit(true)
207    }
208    #[doc = r"Clears the field bit"]
209    #[inline(always)]
210    pub fn clear_bit(self) -> &'a mut W {
211        self.bit(false)
212    }
213    #[doc = r"Writes raw bits to the field"]
214    #[inline(always)]
215    pub fn bit(self, value: bool) -> &'a mut W {
216        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
217        self.w
218    }
219}
220impl W {
221    #[doc = "Bit 0 - SPI Enable"]
222    #[inline(always)]
223    pub fn spien(&mut self) -> SPIEN_W {
224        SPIEN_W { w: self }
225    }
226    #[doc = "Bit 1 - SPI Disable"]
227    #[inline(always)]
228    pub fn spidis(&mut self) -> SPIDIS_W {
229        SPIDIS_W { w: self }
230    }
231    #[doc = "Bit 7 - SPI Software Reset"]
232    #[inline(always)]
233    pub fn swrst(&mut self) -> SWRST_W {
234        SWRST_W { w: self }
235    }
236    #[doc = "Bit 24 - Last Transfer"]
237    #[inline(always)]
238    pub fn lastxfer(&mut self) -> LASTXFER_W {
239        LASTXFER_W { w: self }
240    }
241    #[doc = "Bit 12 - Request to Clear the Comparison Trigger"]
242    #[inline(always)]
243    pub fn reqclr(&mut self) -> REQCLR_W {
244        REQCLR_W { w: self }
245    }
246    #[doc = "Bit 16 - Transmit FIFO Clear"]
247    #[inline(always)]
248    pub fn txfclr(&mut self) -> TXFCLR_W {
249        TXFCLR_W { w: self }
250    }
251    #[doc = "Bit 17 - Receive FIFO Clear"]
252    #[inline(always)]
253    pub fn rxfclr(&mut self) -> RXFCLR_W {
254        RXFCLR_W { w: self }
255    }
256    #[doc = "Bit 30 - FIFO Enable"]
257    #[inline(always)]
258    pub fn fifoen(&mut self) -> FIFOEN_W {
259        FIFOEN_W { w: self }
260    }
261    #[doc = "Bit 31 - FIFO Disable"]
262    #[inline(always)]
263    pub fn fifodis(&mut self) -> FIFODIS_W {
264        FIFODIS_W { w: self }
265    }
266    #[doc = "Writes raw bits to the register."]
267    #[inline(always)]
268    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
269        self.0.bits(bits);
270        self
271    }
272}
273#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_cr](index.html) module"]
274pub struct SPI_CR_SPEC;
275impl crate::RegisterSpec for SPI_CR_SPEC {
276    type Ux = u32;
277}
278#[doc = "`write(|w| ..)` method takes [spi_cr::W](W) writer structure"]
279impl crate::Writable for SPI_CR_SPEC {
280    type Writer = W;
281}
282#[doc = "`reset()` method sets SPI_CR to value 0"]
283impl crate::Resettable for SPI_CR_SPEC {
284    #[inline(always)]
285    fn reset_value() -> Self::Ux {
286        0
287    }
288}
atsams70q21/spi0/spi_cr.rs

atsams70q21/spi0/
spi_cr.rs
